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參數(shù)資料
| 型號： | M39832-T12WNE1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | TRANSZORB, 600W, VR: 25.6V UNIPOLAR, VBR: 28.5V - 31.5V |
| 中文描述： | 單芯片8兆1兆x8或512KB的x16閃存和256千位并行EEPROM存儲(chǔ)器 |
| 文件頁數(shù)： | 18/36頁 |
| 文件大小： | 253K |
| 代理商： | M39832-T12WNE1T |
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Program (PG) Instruction.
This instruction uses
four write cycles. Both for Byte-wide configuration
and for Word-wide configuration. The Program
command A0h is written to address AAAAh in the
Byte-wide configuration or to address 5555h in the
Word-wide configuration on the third cycle after two
Coded cycles. A fourth write operation latches the
Address on the falling edge of W or EF and the Data
to be written on the rising edge and starts the
internal operation. Read operations output the
Status Register bits after the programming has
started. Memory programming is made only by
writing ’0’ in place of ’1’. Status bits DQ6 and DQ7
determine if programming is on-going and DQ5
allows verification of any possible error. Program-
ming at an address not in blocks being erased is
also possible during erase suspend. In this case,
DQ2 will toggle at the address being programmed.
Auto Select (AS) Instruction.
This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address AAAAh
in the Byte-wide configuration or address 5555h in
the Word-wide configuration for command set-up.
A subsequent read will output the manufacturer
code and the device code or the block protection
status depending on the levels of A0 and A1. The
manufacturer code is output when the addresses
lines A0 and A1 are Low, the Flash code for Top
Boot or Bottom Boot is output when A0 is High with
A1 Low.
The AS instruction allows access to the block pro-
tection status. After giving the AS instruction, A0 is
set to V
IL
with A1 at V
IH
, while A12-A18 define the
address of the block to be verified. A read in these
conditions will output a 01h if the block is protected
and a 00h if the block is not protected.
The ERASE in the Flash ARRAY
Flash Array Erase (FAE) Instruction.
This in-
struction uses six write cycles. The Erase Set-up
command 80h is written to address AAAAh in the
Byte-wide configuration or the address 5555h in
the Word-wide configuration on the third cycle after
the two Coded cycles. The Flash Array Erase Con-
firm command 10h is similarly written on the sixth
cycle after another two Coded cycles. If the second
command given is not an erase confirm or if the
Coded cycles are wrong, the instruction aborts and
the device is reset to Read Array. It is not necessary
to program the array with 00h first as it will be done
automatically before erasing it to FFh. Read opera-
tions after the sixth rising edge of W or EF output
the Status Register bits. During the execution of the
erase, Data Polling bit DQ7 returns ’0’, then ’1’ on
completion. The Toggle bits DQ2 and DQ6 toggle
during erase operation and stop when erase is
completed. After completion, the Status Bit DQ5
returns ’1’ if there has been an Erase Failure.
Block Erase (BE) Instruction.
This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address AAAh in
the Byte-wide configuration or address 5555h in
the Word-wide configuration on third cycle after the
two Coded cycles. The Block Erase Confirm com-
mand 30h is similarly written on the sixth cycle after
another two Coded cycles. During the input of the
second command an address within the block to be
erased is given and latched into the memory. Addi-
tional block Erase Confirm commands and block
addresses can be written subsequently to erase
other blocks in parallel, without further Coded cy-
cles. The erase will start after the erase timeout
period (see Erase Timer Bit DQ3 description).
Thus, additional Erase Confirm commands for
other blocks must be given within this delay. The
input of a new Erase Confirm command will restart
the timeout period. The status of the internal timer
can be monitored through the level of DQ3, if DQ3
is ’0’ the Block Erase Command has been given
and the timeout is running, if DQ3 is ’1’, the timeout
has expired and the Block(s) are being erased. If
the second command given is not an erase confirm
or if the Coded cycles are wrong, the instruction
aborts, and the device is reset to Read Array. It is
not necessary to program the block with 00h as it
will be done automatically before erasing it to FFh.
Read operations after the sixth rising edge of W or
EF output the Status Register bits.
During the execution of the erase , the memory
accepts only the Erase Suspend ES and Read/Re-
set RD instructions. Data Polling bit DQ7 returns ’0’
while the erasure is in progress and ’1’ when it has
completed. The Toggle bit DQ2 and DQ6 toggle
during the erase operation. They stop when erase
is completed. After completion the Status bit DQ5
returns ’1’ if there has been an erase failure. In such
a situation, the Toggle bit DQ2 can be used to
determine which block is not correctly erased. In
the case of erase failure, a Read/Reset RD instruc-
tion is necessary in order to reset the memory.
18/36
M39832
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M39832-T15WNE1T | Single Chip 8 Mbit 1Mb x8 or 512Kb x16 Flash and 256 Kbit Parallel EEPROM Memory |
| M39832-B12WNE1T | TVS UNI-DIR 30V 600W DO-15 |
| M39832-B15WNE1T | TVS BI-DIR 30V 600W DO-15 |
| M39832-T12WNE6T | TVS UNI-DIR 33V 600W DO-15 |
| M39832-T15WNE6T | TVS BI-DIR 33V 600W DO-15 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M39832-T12WNE6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 8 Mbit 1Mb x8 or 512Kb x16 Flash and 256 Kbit Parallel EEPROM Memory |
| M39832-T15WNE1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 8 Mbit 1Mb x8 or 512Kb x16 Flash and 256 Kbit Parallel EEPROM Memory |
| M39832-T15WNE6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 8 Mbit 1Mb x8 or 512Kb x16 Flash and 256 Kbit Parallel EEPROM Memory |
| M3986 SL001 | 制造商:Alpha Wire Company 功能描述:CBL 10PR 24AWG SLT 1000' |
| M3986 SL002 | 制造商:Alpha Wire Company 功能描述:CBL 10PR 24AWG SLT 500' |
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