
18
MITSUBISHI MICROCOMPUTERS
3807 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 14. Structure of Interrupt-related registers
b7 b0
b7 b0
b7 b0
b7 b0
b7 b0
Interrupt edge selection register
(INTEDGE : address 003A
16
)
INT
0
interrupt edge selection bit
INT
1
interrupt edge selection bit
INT
2
interrupt edge selection bit
INT
3
interrupt edge selection bit
INT
4
interrupt edge selection bit
Timer 1/INT
2
interrupt source bit
Timer 2/INT
3
interrupt source bit
Timer 3/INT
4
interrupt source bit
0 : Falling edge active
1 : Rising edge active
Interrupt request register 1
(IREQ1 : address 003C
16
)
INT
0
interrupt request bit
INT
1
interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 2/INT
3
interrupt request bit
Timer 3/INT
4
interrupt request bit
Interrupt control register 1
(ICON1 : address 003E
16
)
INT
0
interrupt enable bit
INT
1
interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 2/INT
3
interrupt enable bit
Timer 3/INT
4
interrupt enable bit
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt request register 2
(IREQ2 : address 003D
16
)
CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
Serial I/O2 interrupt request bit
Timer 1/INT
2
interrupt request bit
Timer A interrupt request bit
Timer B interrupt request bit
ADT/AD conversion interrupt request bit
Not used (returns "0" when read)
Interrupt control register 2
(ICON2 : address 003F
16
)
CNTR
0
interrupt enable bit
CNTR
1
interrupt enable bit
Serial I/O2 interrupt enable bit
Timer 1/INT
2
interrupt enable bit
Timer A interrupt enable bit
Timer B interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (returns "0" when read)
(Do not write "1" to this bit)
0 : Interrupt disabled
1 : Interrupt enabled
0 : INT interrupt selected
1 : Timer interrupt selected
Interrupt disable flag I
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
Fig. 13. Interrupt control