參數(shù)資料
型號: M37920FCCHP
廠商: Mitsubishi Electric Corporation
英文描述: Single Chip 16 Bits CMOS Microcomputer(16位單片機)
中文描述: 單片微機16位的CMOS(16位單片機)
文件頁數(shù): 67/158頁
文件大?。?/td> 1261K
代理商: M37920FCCHP
67
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
A-D CONVERTER
The A-D converter is a 10-bit successive approximation converter.
Figure 63 shows the block diagram of the A-D converter, Figure 64
shows the bit configuration of the A-D control register 0 (address
1E
16
), and the bit configuration of the A-D control register 1 (address
1F
16
).
A-D conversion accuracy
Bit 3 of A-D control register 1 is used to select whether to regard the
conversion result as 10-bit or as 8-bit data. The conversion result is
regarded as 10-bit data when bit 3 is “1” and as 8-bit data when bit 3
is “0”.
When the conversion result is used as 10-bit data, the low-order 8
bits of the conversion result is stored in the even-numbered address
of the corresponding A-D register and the high-order 2 bits are
stored in bits 0 and 1 at the odd-numbered address of the corre-
sponding A-D register. Bits 2 to 7 of the A-D register odd-numbered
Fig. 63 Block diagram of A-D converter
address are “000000
2
” when read.
When the conversion result is used as 8-bit data, the conversion re-
sult are stored in even-numbered address of the corresponding A-D
register. In this case, the value at the A-D register’s odd-numbered
address is “00
16
” when read.
A-D conversion frequency
An operation clock (
φ
AD
) of an A-D converter can be selected with bit
7 of the A-D control register 0 and bit 4 of the A-D control register 1.
When bit 4 of the A-D control register 1 is “0”,
φ
AD
becomes f
2
/4
when bit 7 of the A-D control register 0 is “0”,
φ
AD
becomes f
2
/2 when
bit 7 of the A-D control register 0 is “1”.
When bit 4 of the A-D control register 1 is “1”,
φ
AD
becomes f
2
when
bit 7 of the A-D control register 0 is “0”,
φ
AD
becomes f
1
when bit 7 of
the A-D control register 0 is “1”. Note that
φ
AD
= f
1
(in other words,
the fastest speed) can be selected only in the 8-bit mode.
φ
AD
during A-D conversion must be 250 kHz or more because the
comparator uses a capacity coupling amplifier.
Data bus (even)
Selector
Successive approximation register
Decoder
A-D control register 0 (Address 1E
16
)
Resistor ladder network
V
REF
AV
SS
Vref
AN
0
AN
1
AN
2
AN
3
/AD
TRG
Comparator
A-D register 0 (Address 20
16
)
A-D register 1 (Address 22
16
)
A-D register 2 (Address 24
16
)
A-D register 3 (Address 26
16
)
A-D register 0 (Address 21
16
)
A-D register 1 (Address 23
16
)
A-D register 2 (Address 25
16
)
A-D register 3 (Address 27
16
)
Data bus (odd)
A-D control register 1 (Address 1F
16
)
1/2
1/2
f
2
φ
AD
A-D conversion frequency selection
f
1
V
REF
connection select bit
相關(guān)PDF資料
PDF描述
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