
101
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
Watchdog timer
frequency select bit
Writing to watchdog timer register
Watchdog timer
“FFF16” is set.
1/16
1/16
Wf
32
Wf
512
f
2
HLDA
Wait mode
DMA transfer
Watchdog timer
interrupt request
Access to external area
RESET
STP instruction
1
0
1
0
External clock input select bit
Watchdog timer register : address 60
16
Watchdog timer frequency select register : bit 0 at address 61
16
When the most significant bit of the watchdog timer becomes “0”, this signal will be generated.
At the STP instruction execution,
however, Wf
32
is selected
compulsorily.
Disables watchdog timer
WATCHDOG TIMER
The watchdog timer is used to detect unexpected execution se-
quence caused by software runaway and others. Figure 100 shows
the block diagram of the watchdog timer.
The watchdog timer consists of a 12-bit binary counter.
The watchdog timer counts clock Wf
32
, which is obtained by dividing
the peripheral devices’ clock f
2
by 16; or clock Wf
512
, which is ob-
tained by doing it by 256. The watchdog timer frequency select reg-
ister (bit 0 = watchdog timer frequency select bit) shown in Figure
101 selects which clock is to be counted.
Wf
512
is selected when this bit 0 is “0”, and Wf
32
is selected when
this bit 0 is “1”. This bit 0 is cleared to “0” after reset.
FFF
16
is set in the watchdog timer when “L” level voltage is applied
to pin RESET, STP instruction is executed, data is written to the
watchdog timer register (address 60
16
), or the most significant bit of
the watchdog timer becomes “0”.
After FFF
16
is set in the watchdog timer, when the watchdog timer
counts Wf
32
or Wf
512
by 2048 counts, the most significant bit of
watchdog timer becomes “0”, the watchdog timer interrupt request
bit is set to “1”, and FFF
16
is set again in the watchdog timer.
In program coding, make sure that data is written in the watchdog
timer before the most significant bit of the watchdog timer becomes
“0”. If this routine is not executed owing to unexpected program ex-
ecution or others, the most significant bit of the watchdog timer be-
Fig. 100 Block diagram of watchdog timer
Fig. 101
Bit configuration of watchdog timer frequency select register
7
6
5
4
3
2
1
0
Watchdog timer frequency select register
Watchdog timer frequency select bit
0 : Wf
512
is selected.
1 : Wf
32
is selected.
Address
61
16
comes
“
0
”
and an interrupt is generated.
The microcomputer can generate a reset pulse by writing
“
1
”
to bit 6
(software reset bit) of processor mode register 0 in an interrupt rou-
tine and can be restarted.
The watchdog timer can also be used to return from the
STP
state,
where a clock has stopped its operation owing to the
STP
instruction
execution. For details, refer to the sections on the clock generating
circuit.
The watchdog timer stops its operation in the following cases, and at
this time, input to the watchdog timer is disabled:
When the external area is accessed in the hold state
In the wait mode
In the stop mode