
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
40
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
INTERRUPTS
Table 13 shows the interrupt sources and the corresponding inter-
rupt vector addresses. Reset is also described as a type of interrupt
in this section, too.
DBC and BRK instruction are interrupts used only for debugging.
Therefore, do not use these interrupts.
Interrupts other than reset, watchdog timer, zero divide, NMI, and
address matching detection all have interrupt control registers. Table
14 shows the addresses of the interrupt control registers, and Figure
22 shows the bit configuration of the interrupt control register.
The interrupt request bit is automatically cleared by the hardware
during reset or when processing an interrupt. Also, interrupt request
bits other than watchdog timer and NMI can be cleared by software.
Any of INT
2
through INT
0
interrupt requests is generated by an ex-
ternal input.
INT
2
to INT
0
are external interrupts; whether to cause an interrupt at
the input level (level sense) or at the edge (edge sense) can be se-
lected with the level/edge select bit. Furthermore, the polarity of the
interrupt input can be selected with the polarity select bit.
Timer and UART interrupts are described in the respective section.
The priorities of interrupts when multiple interrupt requests are
caused simultaneously are partially fixed by hardware, but, the other
can be adjusted by software as shown in Figure 23.
The hardware priority is fixed as the following:
reset > NMI > watchdog timer > other interrupts
Interrupts
DMA3
DMA2
DMA1
DMA0
Address matching detection interrupt
INT
4
external interrupt
INT
3
external interrupt
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
2
external interrupt
INT
1
external interrupt
INT
0
external interrupt
NMI external interrupt
Watchdog timer
DBC (Do not select.)
Break instruction (Do not select.)
Zero divide
Reset
Table 13 Interrupt sources and interrupt vector addresses
Vector addresses
00FFC0
16
00FFC1
16
00FFC2
16
00FFC3
16
00FFC4
16
00FFC5
16
00FFC6
16
00FFC7
16
00FFCA
16
00FFCB
16
00FFD0
16
00FFD1
16
00FFD2
16
00FFD3
16
00FFD4
16
00FFD6
16
00FFD8
16
00FFDA
16
00FFDC
16
00FFDE
16
00FFE0
16
00FFE2
16
00FFE4
16
00FFE6
16
00FFE8
16
00FFEA
16
00FFEC
16
00FFEE
16
00FFF0
16
00FFF2
16
00FFF4
16
00FFF6
16
00FFF8
16
00FFFA
16
00FFFC
16
00FFFE
16
00FFD5
16
00FFD7
16
00FFD9
16
00FFDB
16
00FFDD
16
00FFDF
16
00FFE1
16
00FFE3
16
00FFE5
16
00FFE7
16
00FFE9
16
00FFEB
16
00FFED
16
00FFEF
16
00FFF1
16
00FFF3
16
00FFF5
16
00FFF7
16
00FFF9
16
00FFFB
16
00FFFD
16
00FFFF
16
Fig. 22 Bit configuration of interrupt control register
7
6
5
4
3
2
1
0
Interrupt priority level
Interrupt request bit
0 : No interrupt requested
1 : Interrupt requested
7
6
5
4
3
2
1
0
Interrupt priority level
Interrupt request bit
0 : No interrupt requested
1 : Interrupt requested
Polarity select bit
0 : Interrupt request bit is set to “1” at “H” level when level sense is selected;
this bit is set to “1” at falling edge when edge sense is selected.
1 : Interrupt request bit is set to “1” at “L” level when level sense is selected;
this bit is set to “1” at rising edge when edge sense is selected.
Level/Edge select bit
0 : Edge sense
1 : Level sense
Bit configuration of interrupt control registers for DMA0 to DMA3, A-D converter, UART0, UART1,
timers A0 to A4, and timers B0 to B2, and INT
3
, INT
4
.
Bit configuration of interrupt control registers for INT
0
– INT
2.