
4: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR
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EPSON
S1D13806 SERIES
APPLICATION NOTES (X28B-G-009-01)
4.3.2 PR31500/PR31700 Host Bus Interface Signals
When the S1D13806 is configured to operate with the PR31500/PR31700, the Host Bus Interface
requires the following signals:
BUSCLK is a clock input required by the S1D13806 Host Bus Interface. It is separate from the
input clock (CLKI) and should be driven by the PR31500/PR31700 bus clock output DCLKOUT.
Address input AB20 corresponds to the PR31500/PR31700 signal ALE (address latch enable)
whose falling edge indicates that the most significant bits of the address are present on the multi-
plexed address bus (AB[12:0]).
Address input AB19 should be connected to the PR31500/PR31700 signal /CARDREG. This sig-
nal is active when either IO or configuration space of the PR31500/PR31700 PC Card slot is being
accessed.
Address input AB18 should be connected to the TX3912 signal CARDIORD*. Either AB18 or the
RD# input must be asserted for a read operation to take place. The presence of two pins which
provide the same function, maps the S1D13806 to both IO and attribute space (see
Section 4.4.3, Address input AB17 should be connected to the TX3912 signal CARDIOWR*. Either AB17 or
the WE0# input must be asserted for a write operation to take place. The presence of two pins
which provide the same function, maps the S1D13806 to both IO and attribute space (see
Section Address inputs AB[16:13] and control inputs M/R#, CS# and BS# must be tied to VDD as they are
not used in this interface mode.
Address inputs AB[12:0], and the data bus DB[15:0], connect directly to the PR31500/PR31700
address and data bus, respectively. MD4 must be set to select the proper endian mode on reset (see
bus naming convention and endian mode, S1D13806 DB[15:8] must be connected to
PR31500/PR31700 D[23:16], and S1D13806 DB[7:0] must be connected to PR31500/
PR31700 D[31:24].
Control inputs WE1# and RD/WR# should be connected to the PR31500/PR31700 signals /
CARDxCSH and /CARDxCSL respectively for byte steering.
Input RD# should be connected to the PR31500/PR31700 signal /RD. Either RD# or the AB18
input (/CARDIORD) must be asserted for a read operation to take place.
Input WE0# should be connected to the PR31500/PR31700 signal /WR. Either WE0# or the
AB17 input (/CARDIOWR) must be asserted for a write operation to take place.
WAIT# is a signal output from the S1D13806 that indicates the host CPU must wait until data is
ready (read cycle) or accepted (write cycle) on the host bus. Since the host CPU accesses to the
S1D13806 may occur asynchronously to the display update, it is possible that contention may
occur in accessing the S1D13806 internal registers and/or display buffer. The WAIT# line
resolves these contentions by forcing the host to wait until the resource arbitration is complete.