參數(shù)資料
型號(hào): M3773S4B
廠商: Mitsubishi Electric Corporation
英文描述: Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī))
中文描述: 單片微機(jī)16位的CMOS(16位單片機(jī))
文件頁數(shù): 21/36頁
文件大?。?/td> 919K
代理商: M3773S4B
21
MITSUBISHI MICROCOMPUTERS
M37733S4BFP
16-BIT CMOS MICROCOMPUTER
New product
Limits
Min.
80
40
40
160
80
80
Max.
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(TB)
t
w(TBH)
t
w(TBL)
TBi
IN
input cycle time (one edge count)
TBi
IN
input high-level pulse width (one edge count)
TBi
IN
input low-level pulse width (one edge count)
TBi
IN
input cycle time (both edges count)
TBi
IN
input high-level pulse width (both edges count)
TBi
IN
input low-level pulse width (both edges count)
ns
ns
ns
ns
ns
ns
Unit
Symbol
Parameter
Timer B input
(Count input in event counter mode)
Limits
Min.
320
160
160
Max.
t
c(TB)
t
w(TBH)
t
w(TBL)
Note.
Limits change depending on f(X
IN
). Refer to “DATA FORMULAS.”
TBi
IN
input cycle time (Note)
TBi
IN
input high-level pulse width (Note)
TBi
IN
input low-level pulse width (Note)
ns
ns
ns
Unit
Symbol
Parameter
Timer B input
(Pulse period measurement mode)
Limits
Min.
320
160
160
Max.
t
c(TB)
t
w(TBH)
t
w(TBL)
Note.
Limits change depending on f(X
IN
). Refer to “DATA FORMULAS.”
TBi
IN
input cycle time (Note)
TBi
IN
input high-level pulse width (Note)
TBi
IN
input low-level pulse width (Note)
ns
ns
ns
Unit
Symbol
Parameter
Timer B input
(Pulse width measurement mode)
Limits
Min.
200
100
100
Max.
t
c(CK)
t
w(CKH)
t
w(CKL)
t
d(C–Q)
t
h(C–Q)
t
su(D–C)
t
h(C–D)
CLK
i
input cycle time
CLK
i
input high-level pulse width
CLK
i
input low-level pulse width
T
X
D
i
output delay time
T
X
D
i
hold time
R
X
D
i
input setup time
R
X
D
i
input hold time
ns
ns
ns
ns
ns
ns
ns
80
0
30
90
Unit
Symbol
Parameter
A-D trigger input
Unit
Symbol
Parameter
Serial I/O
Unit
Symbol
Parameter
____
___
External interrupt
i
input, key input interrupt
i
input
Limits
Min.
250
250
250
Max.
t
w(INH)
t
w(INL)
t
w(KIL)
___
i
input high-level pulse width
___
i
input low-level pulse width
__
i
input low-level pulse width
ns
ns
ns
Limits
Min.
1000
125
Max.
t
c(AD)
t
w(ADL)
input cycle time (minimum allowable trigger)
AD
TRG
input low-level pulse width
ns
ns
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