參數(shù)資料
型號: M3773S4B
廠商: Mitsubishi Electric Corporation
英文描述: Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī))
中文描述: 單片微機(jī)16位的CMOS(16位單片機(jī))
文件頁數(shù): 12/36頁
文件大小: 919K
代理商: M3773S4B
12
MITSUBISHI MICROCOMPUTERS
M37733S4BFP
16-BIT CMOS MICROCOMPUTER
New product
Fig. 11
Relationship between wait bit, wait selection bit, and access time
Wait bit
As shown in Figure 11, when the external memory area is accessed
with the processor mode register 0 (address 5E
16
) bit 2 (wait bit)
cleared to “0”, the access time can be extended compared with no
wait (the wait bit is “1”).
The access time is extended in two ways and this is selected with bit
0 (wait selection bit) of processor mode register 1 (address 5F
16
).
When this bit is “1”, the access time is 1.5 times compared to that for
no wait. When this bit is “0”, the access time is twice compared to
that for no wait.
At reset, the wait bit and the wait selection bit are “0”.
The accessing of internal memory area is performed in no wait mode
regardless of the wait bit.
The processor modes are described below.
Fig. 10 External memory area for each processor mode
(1) Microprocessor mode [10]
Microprocessor mode is entered by connecting the CNVss pin to Vcc
and starting from reset.
_
Signal
E
is output from pin
E
and is “L” during the data/instruction
code read or data write term. When the internal memory area is read
or written,
E
can be fixed to “H” by setting the signal output disable
selection bit (bit 6 of oscillation circuit control register 0) to “1”.
P0
0
/A
0
to P0
7
/A
7
pins become address output pins.
P1
0
/A
8
/D
8
to P1
7
/A
15
/D
15
pins have two functions depending on the
level of the BYTE pin.
When the BYTE pin level is “L”, P1
0
/A
8
/D
8
to P1
7
/A
15
/D
15
pins function
as an address output pin while
E
is “H” and as an odd address data
I/O pin while
E
is “L”. However, if an internal memory is read, external
data is ignored while
E
is “L”.
When the BYTE pin level is “H”, P1
0
/A
8
/D
8
to P1
7
/A
15
/D
15
pins function
as an address output pin.
When the BYTE pin level is “L”, P2
0
/A
16
/D
0
to P2
7
/A
23
/D
7
pins function
as an address output pin while
E
is “H” and as an even address data
I/O pin while
E
is “L”. However, if an internal memory is read, external
data is ignored while
E
is “L”.
R/
W
is a read /write signal which indicates a read when it is “H” and a
___
BHE
is a byte high enable signal which indicates that an odd address
is accessed when it is “L”.
Therefore, two bytes at even and odd addresses are accessed
simultaneously if address A
0
is “L” and
BHE
is “L”.
ALE is an address latch enable signal used to latch the address signal
from a multiplexed signal of address and data. The latch is transparent
while ALE is “H” to let the address signal pass through and held
while ALE is “L”.
80
16
80
16
87F
16
87F
16
SFR
RAM
Evaluation chip
mode
The shaded area is the external memory area.
SFR
00
16
FFFFFF
16
RAM
Microprocessor
mode
FFFFFF
16
2
16
A
16
C
16
Wait bit “1”
(No wait)
Internal clock
Ai/Dj
E
ALE
Ai/Dj
Wait bit “0”
(Wait 1)
E
ALE
Access time
Access time
Address
Data
Address
Data
Address
Data
Address
Data
Ai/Dj
Wait bit “0”
(Wait 0)
E
ALE
Access time
Address
Data
Address
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