參數(shù)資料
型號(hào)： M37735MHBXXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 MM, PLASTIC, QFP-80
文件頁(yè)數(shù)： 32/90頁(yè)
文件大小： 1575K
代理商： M37735MHBXXXFP
38
MITSUBISHI MICROCOMPUTERS
M37735MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
ASYNCHRONOUS SERIAL COMMUNICATION
(UART)
Asynchronous serial communication can be performed using 7-, 8-,
or 9-bit length data. The operation is the same for all data lengths.
The following is the description for 8-bit asynchronous communication.
With 8-bit asynchronous communication, the bits 2 to 0 of the UARTi
transmit/receive mode register must be “101”.
Bit 3 is used to select an internal clock or an external clock. If bit 3 is
“0”, an internal clock is selected and if bit 3 is “1”, then external clock
is selected. If an internal clock is selected, the bit 0 (CS0) and bit 1
(CS1) of UARTi transmit/receive control register 0 are used to select
the clock source. When an internal clock is selected for asynchronous
serial communication, the CLKi pin can be used as a normal port.
If the content of the bit rate generator is n, the selected internal or
external clock is divided by (n + 1), then by 16, and passed through a
control circuit to create the UART transmission clock or the UART
receive clock.
If the selected clock is an internal clock fi or an external clock fEXT,
Bit Rate = (fi or fEXT) / {(n + 1) ! 16}
Bit 4 selects 1 stop bit or 2 stop bits.
The bit 5 is a selection bit of odd parity or even parity.
In the odd parity mode, the parity bit is adjusted so that the sum of
the 1’s in the data and parity bit is always odd.
In the even parity mode, the parity bit is adjusted so that the sum of
the 1’s in the data and parity bit is always even.
Fig. 47 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits is selected
Fig. 46 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit is selected
D6 D7
ST
D1 D2 D3
D4 D5
P SP ST
ST D0 D1
TEi
(1 / f1 , or 1 / fEXT) ! (n + 1) ! 16
Transmission clock
CTSi
Write in transmission buffer register
TIi
TENDi
TXDi
TXEPTYi
Transmission register
← Transmission
buffer register
Stopped because TEi = “0”
Start bit
Parity bit Stop bit
D0
D6 D7
D1 D2 D3 D4 D5
P
SP
D0
TEi
Transmission clock
TIi
TENDi
TXDi
TXEPTYi
(1 / f1 , or 1 / fEXT) ! (n + 1) ! 16
Write in transmission buffer register
Transmission register
← Transmission
buffer register
Stopped because
Start bit
Stop Bit Stop Bit
TEi = “0”
D6
ST
D1 D2 D3 D4 D5
D8 SP
ST D0 D1
D0
D6 D7
D1 D2 D3 D4 D5
SP
D0
D7
SP
D8
ST
D2
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