![](http://datasheet.mmic.net.cn/30000/M37735MHBXXXFP_datasheet_2359980/M37735MHBXXXFP_54.png)
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
51
MITSUBISHI MICROCOMPUTERS
M37735MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fig. 60 Relationship between wait bit, wait selection bit, and access time
Wait bit
As shown in Figure 60, when the external memory area is accessed
with the wait bit (bit 2 of the processor mode register 0 at address
5E16) cleared to “0”, the access time can be extended compared with
no wait (the wait bit is “1”).
The access time is extended in two ways and this is selected with the
wait selection bit (bit 0 of the processor mode register 1 at address
5F16).
When this bit is “1”, the access time is 1.5 times compared to that for
no wait. When this bit is “0”, the access time is twice compared to
that for no wait.
At reset, the wait bit and the wait selection bit are “0”.
The accessing of internal memory area is always performed in the
no wait mode regardless of the wait bit.
The processor modes are described below.
Fig. 59 External memory area for each processor mode
(1) Single-chip mode [00]
Single-chip mode is entered by connecting the CNVss pin to Vss and
starting from reset. Ports P0 to P4 all function as normal I/O ports.
Port P42 can output clock
φ 1 by setting bit 7 of the processor mode
register 0 to “1”. For clock
φ 1, refer to Figure 65.
In this mode, signal E is output from pin E/RDE. Signal E output,
however, can be stopped by setting the signal output disable selection
bit (bit 6 of the oscillation circuit control register 0) to “1” to switch the
E
/RDE pin function to “L” output. Table 7 shows the function of the
signal output disable selection bit.
(2) Memory expansion mode [01]
Memory expansion mode is entered by setting the processor mode
bits to “01” after connecting the CNVss pin to Vss and starting from
reset.
Pin E/RDE becomes the output pin for RDE.
RDE
is a read-enable signal and is “L” during the data read term in
the read cycle. When the internal memory area is read, RDE can be
fixed to “H” by setting the signal output disabe selection bit (bit 6 of
the oscillation circuit control register) to “1”.
Ports P06 and P07 become the output pins for addresses A16 and
A17, respectively. Similarly, port P05 becomes the output pin for RSMP,
and ports P00 to P04 become the output pins for CS0 to CS4,
respectively. In this case, their functions as I/O ports are lost.
Wait bit “0”
(Wait 0)
Wait bit “0”
(Wait 1)
Wait bit “1”
(No wait)
Internal clock
Port P2
RDE
or
WEL
, WEH
ALE
Port P2
RDE
or
WEL
, WEH
ALE
Access time
Address
Data Address Data
Address
Data
Address
Data
Port P2
RDE
or
WEL
, WEH
ALE
Access time
Address
Data
Address
SFR
RAM
Microprocessor
mode
The shaded area is the external memory area.
Note that banks 1016 to FF16 cannot be accessed.
SFR
0016
8016
FFFFFF16
RAM
ROM
Memory expansion
mode
FFF16
1FFFF16