參數(shù)資料
型號(hào)： M37735MHBXXXFP
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù)： 27/93頁(yè)
文件大?。?/td> 1802K
代理商： M37735MHBXXXFP
30
MITSUBISHI MICROCOMPUTERS
M37735MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
UART 0 transmit/receive mode register 3016
UART 1 transmit/receive mode register 3816
Addresses
Serial I/O mode selection bits
0 0 0 : Parallel port
0 0 1 : Clock synchronous
1 0 0 : 7-bit UART
1 0 1 : 8-bit UART
1 1 0 : 9-bit UART
765 43 2 1 0
Internal clock/External clock selection bit
0 : Internal clock
1 : External clock
Stop bit length selection bit
0 : 1 stop bit
1 : 2 stop bits
Odd/even parity selection bit
0 : Odd parity
1 : Even parity
Parity enable bit
0 : No parity
1 : With parity
Sleep function selection bit
0 : No sleep
1 : Sleep
Data bus (odd)
Data bus (even)
Bit converter
0
0 000
00
D7 D6 D5 D4 D3 D2 D1 D0
D8
Receive register
Receive
buffer register
UART0 (Addresses 3716, 3616)
UART1 (Addresses 3F16, 3E16)
UART2 (Addresses 6B16, 6A16)
Receive control
circuit
RxDi
Data bus (even)
D7 D6 D5 D4 D3 D2 D1 D0
D8
Transmisson register
UART0 (Addresses 3316, 3216)
UART1 (Addresses 3B16, 3A16)
UART2 (Addresses 6716, 6616)
control circuit
Transmission
Bit converter
Transmission
buffer register
Polarity
reversing circuit
f 2
f 16
f 64
f 512
CLKi
CTSi/RTSi
1/16 Divider
UART receive
Clock synchronous
1/16 Divider
Clock synchronous
1/2 Divider
Clock synchronous
(Internal clock)
Clock synchronous
(External clock)
1/(n + 1)
Divider
External
Internal
Clock source selection
Bit rate
generator
UART0
(Address 3116)
UART1
(Address 3916)
UART2
(Address 6516)
Receive clock
Transmission clock
Data bus (odd)
TxDi
Clock synchronous
(Internal clock)
UART transmission
(Note)
Note. UART2 does not include the bit converter, the polarity
reversing circuit and the RTSi output.
UART 2 transmit/receive mode register 6416
Address
Serial I/O mode selection bits
0 0 0 : Parallel port
0 0 1 : Clock synchronous
1 0 0 : 7-bit UART
1 0 1 : 8-bit UART
1 1 0 : 9-bit UART
6 543 2 1 0
Internal clock/External clock selection bit
0 : Internal clock
1 : External clock
Stop bit length selection bit
0 : 1 stop bit
1 : 2 stop bits
Odd/even parity selection bit
0 : Odd parity
1 : Even parity
Parity enable bit
0 : No parity
1 : With parity
The switch of A-D conversion interrupt and UART2 transmit/receive
interrupt is performed by bits 0 to 2. When selecting a parallel port, A-D
conversion interrupt is valid. When selecting a clock synchronous serial
I/O port or a UART, UART2 transmit/receive interrupt is valid.
Note.
7
SERIAL I/O PORTS
Three independent serial I/O ports are provided.
Figure 36 shows a block diagram of the serial I/O ports.
Table 5 shows the functional differences of three serial I/O ports
(UART 0, 1, 2).
Bits 0, 1, and 2 of the UARTi (i = 0, 1, 2) transmit/receive mode
register shown in Figure 37 are used to determine whether to use
port P8 or port P7 as a parallel port, a clock synchronous serial I/O
port, or an asynchronous serial I/O port (UART) using start and stop
bits.
Fig. 36 Serial I/O port block diagram
Fig. 37 UARTi transmit/receive mode register bit configuration
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