參數(shù)資料
型號: M37548G3FP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO20
封裝: 4.40 X 6.50 MM, 0.65 MM PITCH, PLASTIC, LSSOP-20
文件頁數(shù): 84/84頁
文件大?。?/td> 1427K
代理商: M37548G3FP
Rev.2.02
Mar 31, 2009
Page 9 of 81
REJ03B0210-0202
7548 Group
Fig 6.
Register push and pop at interrupt generation and subroutine call
Interrupt request
(Note)
M(S)
←(PCH)
(S)
←(S) 1
M(S)
←(PCL)
(
S)
(S) 1
....
.
Execute RTS
Subroutine
(S)
←(S) + 1
(PCL)
←M(S)
(S)
←(S) + 1
(PCH)
←M(S)
M(S)
←(PCH)
(S)
←(S) 1
M(S)
←(PCL)
(S)
←(S) 1
M(S)
←(PS)
(S)
←(S) 1
Interrupt
Service Routine
(S)
←(S) + 1
(PS)
←M(S)
(S)
←(S) + 1
(PCL)
←M(S)
(S)
←(S) + 1
(PCH)
←M(S)
Execute JSR
..
...
Execute RTI
Store Return Address
on Stack
Store Contents of
Processor
Status Register on Stack
I Flag “0” to “1”
Fetch the Jump Vector
Restore Contents of
Processor Status Register
Restore Return
Address
Restore Return
Address
Store Return
Address
on Stack
Note : The condition to enable the interrupt
→ Interrupt enable bit is “1”
Interrupt disable flag is “0”
On-going Routine
Table 4
Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PLA
Processor status register
PHP
PLP
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參數(shù)描述
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