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| 型號： | M37548G3FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 4.40 X 6.50 MM, 0.65 MM PITCH, PLASTIC, LSSOP-20 |
| 文件頁數(shù)： | 24/84頁 |
| 文件大小： | 1427K |
| 代理商： | M37548G3FP |
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Rev.2.02
Mar 31, 2009
Page 30 of 81
REJ03B0210-0202
7548 Group
Output compare
7548 group has 3-output compare channels. Each channel (0 to
2) has the same function and can be used to output waveform by
using count value of Timer A.
Three output compare channels share the registers with the input
capture (one channel), but their individual circuits operate
independently so that all the channels can be used at the same
time.
To use each compare channel, set “1” to the compare x (x = 0, 1,
2) output port selection bit and set the port direction register
corresponding to compare channel to output mode.
The compare value for each channel is set to the capture/compare
register (low-order) and capture/compare register (high-order).
Writing to the register for each channel is controlled by setting
value of capture/compare register RW pointer. Writing to each
register is in the following order;
1. Set the corresponding compare latch to the capture/compare
register RW pointer.
2. Write a value to the capture/compare register (low-order)
and capture/compare register (high-order). (It doesn’t care
even if either low-order or high-order is written early.)
3. Set “1” to the compare latch y (y = 00, 01, 10, 11, 20, 21)
re-load bit.
When “1” is set to the compare latch y re-load bit, the value set to
the compare register is loaded to compare latch when the next
timer underflow.
After loading, re-load bit is set to “0” automatically.
When the count value of timer A matches the compare latch
setting value, a trigger to the compare output circuit is generated.
The trigger can be enabled or disabled using the compare x
trigger enable bit. When the compare x trigger enable bit is set to
1, the output waveform from the port is as follows.
When the value of the compare x output level latch is “0”
High level at compare latch x0 match
Low level at compare latch x1 match
When the value of the compare x output level latch is “1”
Low level at compare latch x0 match
High level at compare latch x1 match
The output waveform does not change if the compare x trigger
enable bit is set to 0, so the port output remains fixed at high or
low level.
The compare output level of each channel can be confirmed by
reading the compare x output status bit.
Compare interrupt is available when match of each compare
channel and timer count value. The interrupt request from each
channel can be disabled or enabled by setting value of compare
latch y interrupt source bit.
Notes
(1) If timer A is stopped, when a value is written to the capture/
compare register it is immediately transferred to the
compare latch. In addition, if timer A is stopped and the
compare x trigger enable bit is set to “1”, the output latch is
initialized.
(2) Do not write the same data to both of compare latch x0 and
x1.
(3) When setting value of the compare latch is larger than timer
setting value, compare match signal is not generated.
Accordingly, the output waveform is fixed to “L” or “H”
level.
However, when setting value of another compare latch is
smaller than timer setting value, this compare match signal
is generated. Accordingly, compare interrupt occurs.
(4) When the compare x trigger enable bit is cleared to “0”
(disabled), the match trigger to the waveform output circuit
is disabled, and the output waveform can be fixed to “L” or
“H” level.
However, in this case, the compare match signal is
generated.
Accordingly, compare interrupt occurs.
Fig 30. Structure of capture/compare register
Fig 31. Structure of capture/compare register RW
pointer
Fig 32. Structure of compare register re-load register
Fig 33. Structure of capture/compare port register
b7
b0
Capture/Compare register (low-order)
(CRAL: address 001016, initial value: 0016)
b7
b0
Capture/Compare register (high-order)
(CRAH: address 001116, initial value: 0016)
b7
b0
Capture/Compare register RW pointer
(CCRP: address 001216, initial value: 0016)
Capture/Compare register RW pointer
b2 b1 b0
0 0 0 : Compare latch 00
0 0 1 : Compare latch 01
0 1 0 : Compare latch 10
0 1 1 : Compare latch 11
1 0 0 : Compare latch 20
1 0 1 : Compare latch 21
1 1 0 : Capture latch 00
1 1 1 : Capture latch 01
Not used (returns “0” when read)
b7
b0
Compare register re-load register
(CMPR: address 002D16, initial value: 0016)
Compare latch 00, 01 re-load bit
0: Re-load disabled
1: Re-load at next underflow
Compare latch 10, 11 re-load bit
0: Re-load disabled
1: Re-load at next underflow
Compare latch 20, 21 re-load bit
0: Re-load disabled
1: Re-load at next underflow
Not used (returns “0” when read)
b7
b0
Capture/Compare port register
(CCPR: address 002E16, initial value: 0016)
Capture 0 input port selection bit
0: Capture from P03
1: Low-speed on-chip oscillator/16
Compare 0 output port selection bit
0: P10 is I/O port
1: P10 is Compare 0 output
Compare 1 output port selection bit
0: P11 is I/O port
1: P11 is Compare 1 output
Compare 2 output port selection bit
0: P12 is I/O port
1: P12 is Compare 2 output
Not used (returns “0” when read)
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相關(guān)代理商/技術(shù)參數(shù) |
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| M37548G3FP#U0 | 功能描述:MCU 6K ROM 256K 20-SSOP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 標準包裝:250 系列:LPC11Uxx 核心處理器:ARM? Cortex?-M0 芯體尺寸:32-位 速度:50MHz 連通性:I²C，Microwire，SPI，SSI，SSP，UART/USART，USB 外圍設(shè)備:欠壓檢測/復位，POR，WDT 輸入/輸出數(shù):40 程序存儲器容量:96KB（96K x 8） 程序存儲器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):1.8 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-LQFP 包裝:托盤 其它名稱:568-9587 |
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| M37549G1FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37549G1-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37549G2FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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