25
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Bias Control and Time Division Control
The LCD controller/driver has built-in bias resistor and supports 1/
4 bias or 1/5 bias. The bias setting is made by either floating pins
VL2 and VL3 (1/5 bias) or shorting them together externally (1/4
bias). The number of common pins driven is determined by the
duty ratio selected. Bits 0 and 1 of the LCD mode register are
used to set the duty ratio.
Contrast Controller
The contrast controller is a circuit generating 32 steps of voltages
using the voltage applied to the VLCD pin as the reference voltage.
The voltage generated varies depending on the values given to bit
0–bit 4 with the LCD contrast control register. When bit 7 of the
LCD contrast control register is set to “1”, the voltage generated by
the contrast controller is applied to VL5. Given below is the relation
between the values set to bit 0–bit 4 of LCD contrast control regis-
ter and the voltages applied to VL5.
Voltage applied to VL5
= Voltage applied to the VLCD pin ! (n+33)/64
Where:
n = Value set to bit 0–bit 4 of the LCD contrast control register (in
decimal values)
Duty
ratio
1/8
1/11
1/16
Duty ratio selection bit
Bit 1
0
1
Bit 0
0
1
0
1
Common pins used
COM0–COM7
COM8–COM15
COM0–COM10
COM0–COM15
When the contrast controller is used, it becomes possible to apply
32 steps of voltage to VL5 from 1/2 VLCD through VLCD. Conse-
quently, 32 steps of contrast adjustment by the software becomes
possible.
Note: Supply power to the contrast controller from an external source
through the VLCD pin.
Also, when bit 7 of the LCD contrast control register is set to “0”,
VLCD pin is coupled directly to VL5 (the contrast controller and VL5
become separated). In this case, perform contrast adjustment using
an external circuit.
Note: For all duty ratios, the unused common pins output the non-select
waveform.
Fig. 22 Structure of LCD contrast control register
LCD Drive Timing
The LCD controller/driver supports both type-A and type-B drive
timing.
The desired type is selected by setting the LCD drive timing selec-
tion bit (bit 4 of the LCD mode register).
If the LCD drive timing selection bit is set to “0”, type-A is selected,
and if this bit is set to “1”, type-B is selected. After reset, type-A is
selected for the drive timing.
The frame frequency can be determined by the following equation:
Frame frequency =
Fig. 21 Example of circuit at 1/5 and 1/4 bias
Table 3 Time division control
LCDCK count source frequency
LCDCK division ratio ! duty ratio
VL5
R
VL4
R
VL3
R
VL2
R
VL1
R
VL2
VL3
Contrast
controller
“0”
“1”
LCD contrast control enable bit
Variable
resistance
for
brightness
control
Open
VLCD
1/5 bias
Variable resistance
for
brightness control
VL5
R
VL4
R
VL3
R
VL2
R
VL1
R
VL2
VL3
Contrast
controller
“0”
“1”
LCD contrast control enable bit
External
connection
VLCD
1/4 bias
LCD contrast control register
(LC : address 003716)
VLCD level selection bit
Not used (returns “0” when read)
LCD contrast control enable bit
0 : Built-in LCD contrast
controller is not used
1 : Built-in LCD contrast
controller is used.
b7
b0