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參數資料
| 型號： | M37510E6-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQFP176 |
| 封裝： | PLASTIC, QFP-176 |
| 文件頁數： | 11/43頁 |
| 文件大小： | 614K |
| 代理商： | M37510E6-XXXFP |
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19
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer,
but the two buffers have the same address in memory.
Since the shift register cannot be written to or read from directly,
transmit data is written to the transmit buffer, and receive data is
read from the receive buffer. The transmit buffer can also hold the
next data to be transmitted, and the receive buffer can hold a char-
acter while the next character is being received.
Fig. 15 Block diagram of UART serial I/O
Fig. 16 Operation of UART serial I/O function
Data bus
Receive buffer
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Serial I/O control register
Receive shift register
Clock control circuit
P44/RXD1
P30/RXD2
Address 001A16
003216
Address
001816
003016
UART control register
Address 001B16
003316
SP detector
PE FE
7 bits
8 bits
Character length selection bit
OE
P46/SCLK1
P32/SCLK2
f(XIN)
P45/TXD1
P31/TXD2
Baud rate generator
Address 001C16 003416
1/4
BRG count source selection bit
Frequency division ratio 1/(n+1)
1/16
Serial I/O synchronous clock selection bit
Character length selection bit
Transmit shift register
Transmit buffer register
Transmit interrupt source selection bit
Transmit shift completion flag (TSC)
Transmit interrupt request (TI)
Serial I/O status register
Address
Data bus
Contents in
are for serial I/O2.
001816 003016
Transmit buffer empty flag (TBE)
Address 001916 003116
1/16
ST detector
ST/SP/PA generator
D0
D1
TBE = 1
SP
ST
D0
D1
ST
SP
TSC = 1 V
TBE = 0
TSC = 0
TBE = 1
1 start bit
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit(s)
V Generated at 2nd bit in 2-stop-bit mode
RBF = 0
D0
D1
RBF = 1
SP
ST
D0
D1
ST
SP
RBF = 1
Transmit or receive clock
Transmit buffer write signal
Serial output TXD
Receive buffer read signal
Serial input RXD
Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O control register.
The receive interrupt (RI) is set when the RBF flag becomes “1”.
After data is written to the transmit buffer when TSC = 1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC = 0.
Notes 1 :
2 :
3 :
4 :
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