參數(shù)資料
型號： M37510E6-FS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CQCC160
封裝： WINDOWED, GLASS SEALED, LCC-160
文件頁數(shù)： 33/43頁
文件大?。?/td> 614K
代理商： M37510E6-FS
39
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Symbol
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
tsu(RXD1–SCLK1)
tsu(RXD2–SCLK2)
th(SCLK1–RXD1)
th(SCLK2–RXD2)
TIMING REQUIREMENTS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85
°C, unless otherwise noted)
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0, INT1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0, INT1 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O2 input set up time
Serial I/O1 input hold time
Serial I/O2 input hold time
Limits
Min.
2
125
50
200
80
800
370
220
100
Typ.
Max.
Unit
s
ns
Note: When f(
φ) = 4 MHz and bit 6 of address 001A16 or 003216 is “1” (clock synchronous). Divide this value by four when f(φ) = 4 MHz and bit 6 of address
001A16 or 003216 is “0” (clock asynchronous).
Symbol
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
tsu(RXD1–SCLK1)
tsu(RXD2–SCLK2)
th(SCLK1–RXD1)
th(SCLK2–RXD2)
TIMING REQUIREMENTS 2 (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85
°C, unless otherwise noted)
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0, INT1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0, INT1 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O2 input set up time
Serial I/O1 input hold time
Serial I/O2 input hold time
Limits
Min.
2
500
200
500
230
2000
950
400
200
Typ.
Max.
Unit
s
ns
Note: When f(
φ) = 1 MHz and bit 6 of address 001A16 or 003216 is “1” (clock synchronous). Divide this value by four when f(φ) = 1 MHz and bit 6 of address
001A16 or 003216 is “0” (clock asynchronous).
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