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參數(shù)資料
| 型號： | M37510E6-FS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CQCC160 |
| 封裝： | WINDOWED, GLASS SEALED, LCC-160 |
| 文件頁數(shù)： | 28/43頁 |
| 文件大?。?/td> | 614K |
| 代理商： | M37510E6-FS |
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34
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal operation mode (D) flag because of their effect on calcu-
lations.
Interrupts
The contents of the interrupt request bits do not change immedi-
ately after they have been written.
After writing to an interrupt request register, execute at least one
instruction before performing a BBC or BBS instruction.
Decimal Calculations
To calculate in decimal notation, set the decimal operation mode
flag (D) to “1”, then execute the ADC or the SBC instruction. Only
the ADC and the SBC instruction yield proper decimal results. Af-
ter executing the ADC or SBC instruction, execute at least one
instruction before executing the SEC, the CLC, or the CLD instruc-
tion.
In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flag are invalid. The carry flag can be used to indicate
whether a carry or borrow has occurred.
Initialize the carry flag before each calculation. Clear the carry flag
before the ADC instruction and set the flag before the SBC in-
struction.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Multiplication and Division Instructions
The index X mode (T) and the decimal mode (D) flag do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
qthe data transfer instruction (LDA, etc.)
qthe operation instruction when the index X mode flag (T) is “1”
qthe addressing mode which uses the value of a direction register
as an index
qthe bit-test instruction (BBC or BBS, etc.) to a direction register
qthe read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1”.
Serial I/O continues to output the final bit from the TXD pin after
transmission is completed.
Instruction Execution Time
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock
φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
In high-speed mode, the frequency of the internal clock
φ is half of
the XIN frequency.
In middle-speed mode, the frequency of the internal clock
φ is one
eighth the XIN frequency.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
1. Mask ROM Order Confirmation Form
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical
copies)
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