參數(shù)資料
型號(hào): M37281EKSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP52
封裝: 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-52
文件頁(yè)數(shù): 123/172頁(yè)
文件大?。?/td> 1319K
代理商: M37281EKSP
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M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
Rev.1.01
2003.07.16
page 54 of 170
Fig. 8.9.2 ROM Correction Enable Register
Fig. 8.9.1 ROM Correction Address Registers
8.9 ROM CORRECTION FUNCTION
This can correct program data in ROM. Up to 2 addresses can be
corrected, a program for correction is stored in the ROM correction
vector in RAM as the top address. The ROM correction vectors are 2
vectors.
Vector 1 : address 02C016
Vector 2 : address 02E016
Set the address of the ROM data to be corrected into the ROM cor-
rection address register. When the value of the counter matches the
ROM data address in the ROM correction vector as the top address,
the main program branches to the correction program stored in the
ROM memory for correction. To return from the correction program
to the main program, the op code and operand of the JMP instruction
(total of 3 bytes) are necessary at the end of the correction program.
The ROM correction function is controlled by the ROM correction
enable register.
Notes 1: Specify the first address (op code address) of each instruction as the
ROM correction address.
2: Use the JMP instruction (total of 3 bytes) to return from the correction
program to the main program.
3: Do not set the same ROM correction address to vectors 1 and 2.
4: For the M37281MKH-XXXSP and M37281EKSP, when using the ex-
pansion ROM (BK7 = “1”), the ROM correction function do not oper-
ate used for addresses 100016 to1FFF16. Note that on programming.
020C16
ROM correction address 1 (high-order)
020D16
ROM correction address 1 (low-order)
020E16
ROM correction address 2 (high-order)
020F16
ROM correction address 2 (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
ROM correction enable register (RCR) [Address 021016]
B
After reset RW
ROM Correction Enable Register
0
Vector 1 enable bit (RCR0)
Name
Functions
0: Disabled
1: Enabled
1
Vector 2 enable bit (RCR1)
0: Disabled
1: Enabled
4
to
7
Nothing is assigned. These bits are write disable bits. When
these bits are read out, the values are “0.”
0
RW
R —
0
2, 3 Fix these bits to “0.”
0
RW
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