參數(shù)資料
型號(hào)： M37274MA-084SP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 61/147頁
文件大?。?/td> 2042K
代理商： M37274MA-084SP
61
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
(9) START/STOP Condition Detect Conditions
The START/STOP condition detect conditions are shown in Figure
52 and Table 9. Only when the 3 conditions of Table 9 are satisfied,
a START/STOP condition can be detected.
Note:
When a STOP condition is detected in the slave mode
(MST = 0), an interrupt request signal “IICIRQ” is generated
to the CPU.
(8) STOP Condition Generation Method
When the ES0 bit of the I
2
C control register (address 00F9
16
) is “1,”
execute a write instruction to the I
2
C status register (address 00F8
16
)
for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A
STOP condition will then be generated. The STOP condition genera-
tion timing and the BB flag reset timing are different in the standard
clock mode and the high-speed clock mode. Refer to Figure 51 for
the STOP condition generation timing diagram, and Table 8 for the
START condition/STOP condition generation timing table.
Fig. 59. STOP Condition Generation Timing Diagram
Fig. 60. START Condition/STOP Condition Detect Timing
Diagram
Standard Clock Mode
6.5 μs (26 cycles) <
SCL
release time
3.25 μs (13 cycles) < Setup time
3.25 μs (13 cycles) < Hold time
Note:
Absolute time at
φ
= 4 MHz. The value in parentheses de-
notes the number of
φ
cycles.
High-speed Clock Mode
1.0 μs (4 cycles) <
SCL
release time
0.5 μs (2 cycles) < Setup time
0.5 μs (2 cycles) < Hold time
Table 9. START Condition/STOP Condition Detect Conditions
Table 8. START Condition/STOP Condition Generation Timing
Table
Item
Setup time
Hold time
Set/reset time
for BB flag
Note:
Absolute time at
φ
= 4 MHz. The value in parentheses de-
notes the number of
φ
cycles.
Standard Clock Mode
5.0 μs (20 cycles)
5.0 μs (20 cycles)
3.0 μs (12 cycles)
High-speed Clock Mode
2.5 μs (10 cycles)
2.5 μs (10 cycles)
1.5 μs (6 cycles)
I
2
C status register
write signal
Reset time for
BB flag
Hold time
Setup
time
SCL
SDA
BB flag
Hold time
Setup
time
SCL
SDA
(START condition)
SDA
(STOP condition)
SCL release time
Hold time
Setup
time
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