參數(shù)資料
型號(hào)： M37274MA-084SP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 46/147頁
文件大?。?/td> 2042K
代理商： M37274MA-084SP
46
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
After a falling of the clock run-in pulse set in bits 2 to 0 of clock run-
in detect register 2 (address 00E9
16
) is detected, a start bit is
detected by sampling a comparator output. A sampling clock for
sampling is obtained by dividing the reference clock generated in
the timing signal generating circuit by 13.
Fig. 41. Clock Run-in Register 2
Fig. 42. Clock Run-in Detect Register 2
Figure 42 shows the structure of clock run-in detect register 2.
The contents of bits 2 to 0 of clock run-in detect register 2 and bit
1 of clock run-in register 2 are written at a falling of the horizontal
synchronous signal. For this reason, even if an instruction for setting
is executed, the contents of the register cannot be rewritten until a
falling of the horizontal synchronous signal.
b7 b6 b5 b4 b3 b2 b1 b0
Clock run-in register 2 (CR2) [Address 00E7
16
]
Clock Run-in Register 2
0
R W
0
R W
0,
2 to 4,
7
Fix these bits to “1.”
B
After reset
Functions
Name
R W
0
0
1
0
R W
5, 6
Fix these bits to “0.”
1
1
1
1
1
Start bit detecting
method selection bit
(CR21)
0: Method 1
1: Method 2
b7 b6 b5 b4 b3 b2 b1 b0
Clock run-in detect register 2 (CRD2) [Address 00E9
16
]
Clock Run-in Detect Register 2
B
After reset
Functions
Name
R W
0
R W
0
to
2
0
R W
Clock run-in pulses for
sampling
(CRD20 to CRD22)
3
to
7
Data clock generating
time
(CRD23 to CRD27)
b2 b1 b0
0 0 0 : Not available
0 0 1 : 1st pulse
0 1 0 : 2nd pulse
0 1 1 : 3rd pulse
1 0 0 : 4th pulse
1 0 1 : 5th pulse
1 1 0 : 6th pulse
1 1 1 : 7th pulse
Time from detection of a start
bit to occurrence of a data clock
= (13 + set value)
reference clock period
2
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