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參數(shù)資料
| 型號(hào)： | M37274MA-084SP |
| 廠(chǎng)商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| 中文描述： | 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器 |
| 文件頁(yè)數(shù)： | 41/147頁(yè) |
| 文件大?。?/td> | 2042K |
| 代理商： | M37274MA-084SP |
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41
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
Fig. 36. Vsep Generating Timing (method 2)
Composite
sync signal
Timing
signal
V
sep
signal
A V
sep
signal is generated at a rising of the timing signal
immediately after the “L” level width of the composite
sync signal exceeds a certain time.
Measure “L” period
(3) Synchronous Signal Separation Circuit
This circuit separates a horizontal synchronous signal and a vertical
synchronous signal from the composite sync signal taken out in the
sync slice circuit.
Horizontal synchronous signal (H
sep
)
A one-shot horizontal synchronous signal Hsep is generated at
the falling edge of the composite sync signal.
Vertical synchronous signal (V
sep
)
As a V
sep
signal generating method, it is possible to select one of
the following 2 methods by using bit 7 of the sync slice register
(address 00E3
16
).
Method 1
The “L” level width of the composite sync signal is
measured. If this width exceeds a certain time, a V
sep
signal is generated in synchronization with the rising
of the timing signal immediately after this “L” level.
Method 2
The “L” level width of the composite sync signal is
measured. If this width exceeds a certain time, it is
detected whether a falling of the composite sync
signal exits or not in the “L” level period of the timing
signal immediately after this “L” level. If a falling exists,
a V
sep
signal is generated in synchronization with
the rising of the timing signal (refer to Figure 36).
Figure 36 shows a V
sep
generating timing. The timing signal shown
in the figure is generated from the reference clock which the timing
generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating
the shape of the V-pulse portion of the composite sync signal. As
shown in Figure 38, when the A level matches the B level, this bit is
“0.” In the case of a mismatch, the bit is “1.”
For the pins RVCO and the HLF, connect a resistor and a capacitor
as shown in Figure 31. Make the length of wiring which is connected
to these pins as short as possible so that a leakage current may not
be generated.
Note:
It takes a few tens of milliseconds until the reference clock
becomes stable after the data slicer and the timing signal
generating circuit are started. In this period, various timing
signals, H
sep
signals and V
sep
signals become unstable. For
this reason, take stabilization time into consideration when
programming.
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