參數(shù)資料
型號： M37274MA-084SP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 134/147頁
文件大?。?/td> 2042K
代理商： M37274MA-084SP
134
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Interrupt Request Register 1
CPU Mode Register
Address 00FB
16
Address 00FC
16
b7b6 b5b4b3 b2b1b0
1
B
After reset
R W
0
CPU Mode Register
0, 1
2
3, 4
1
1
0
0
Name
Functions
Processor mode bits
(CM0, CM1)
0 0: Single-chip mode
0 1:
1 0: Not available
1 1:
Fix these bits to “1.”
1
Stack page selection
bit (CM2)
(See note)
1
b1 b0
0: 0 page
1: 1 page
0
0
5
6
Main Clock (X
IN
–X
OUT
)
stop bit
(CM6)
CPU mode register (CPUM) (CM) [Address FB
16
]
R W
R W
R W
R W
R W
X
COUT
drivability
selection bit (CM5)
0: LOW drive
1: HIGH drive
0: Oscillating
1: Stopped
7
Internal system clock
selection bit
(CM7)
R W
0: X
IN
–X
OUT
selected
(high-speed mode)
1: X
CIN
–X
COUT
selected
(high-speed mode)
Note:
This bit is set to “1” after the reset release.
b7b6 b5b4b3 b2b1b0
Interrupt request register 1 (IREQ1) [Address 00FC
B
0
Name
Functions
After reset
R W
0
Interrupt Request Register 1
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt
request bit (TM1R)
Timer 2 interrupt
request bit (TM2R)
Timer 3 interrupt
request bit (TM3R)
Timer 4 interrupt
request bit (TM4R)
OSD interrupt request
bit (CRTR)
V
SYNC
interrupt
request bit (VSCR)
A-D conversion INT3
interrupt request bit (ADR)
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
1
2
3
4
5
6
7
0
0
8
0
8
0
8
0
8
0
8
0
8
8
8
: “0” can be set by software, but “1” cannot be set.
—
16
]
R
R
R
R
R
R
R
R
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