參數(shù)資料
型號(hào)： M37274MA-053SP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁(yè)數(shù)： 59/147頁(yè)
文件大?。?/td> 2042K
代理商： M37274MA-053SP
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59
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
I
Bit 6: Communication Mode Specification Bit (transfer direction
specification bit: TRX)
This bit decides the direction of transfer for data communication. When
this bit is “0,” the reception mode is selected and the data of a trans-
mitting device is received. When the bit is “1,” the transmission mode
is selected and address data and control data are output into the
SDA in synchronization with the clock generated on the SCL.
When the ALS bit of the I
2
C control register (address 00F9
16
) is “0”
in the slave reception mode is selected, the TRX bit is set to “1”
(transmit) if the least significant bit (R/W bit) of the address data trans-
mitted by the master is “1.” When the ALS bit is “0” and the R/W bit is
“0,” the TRX bit is cleared to “0” (receive).
The TRX bit is cleared to “0” in one of the following conditions.
When arbitration lost is detected.
When a STOP condition is detected.
When occurence of a START condition is disabled by the START
condition duplication prevention function (Note).
With MST = “0” and when a START condition is detected.
With MST = “0” and when ACK non-return is detected.
At reset
I
Bit 7: Communication Mode Specification Bit (master/slave speci-
fication bit: MST)
This bit is used for master/slave specification for data communica-
tion. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are re-
ceived, and data communication is performed in synchronization with
the clock generated by the master. When this bit is “1,” the master is
specified and a START condition and a STOP condition are gener-
ated, and also the clocks required for data communication are gen-
erated on the SCL.
The MST bit is cleared to “0” in one of the following conditions.
Immediately after completion of 1-byte data transmission when ar-
bitration lost is detected
When a STOP condition is detected.
When occurence of a START condition is disabled by the START
condition duplication preventing function (Note).
At reset
Note:
The START condition duplication prevention function disables
the START condition generation, reset of bit counter reset,
and SCL output, when the following condition is satisfied:
a START condition is set by another master device.
Fig. 56. I
2
C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I
2
C status register (S1) [Address 00F8
16
]
I
2
C Status Register
0
3
4
5
6, 7
b7 b6
0 0 : Slave recieve mode
0 1 : Slave transmit mode
1 0 : Master recieve mode
1 1 : Master transmit mode
1
2
0
0
0
0
0
B
Name
Functions
After reset
R W
Communication mode
specification bits
(TRX, MST)
0 : Bus free
1 : Bus busy
Bus busy flag (BB)
0 : Interrupt request issued
1 : No interrupt request issued
I
2
C-BUS interface interrupt
request bit (PIN)
0 : Not detected
1 : Detected
Arbitration lost detecting flag
(AL) (See note)
0 : Address mismatch
1 : Address match
Slave address comparison
flag (AAS) (See note)
0 : No general call detected
1 : General call detected
General call detecting flag
(AD0)
(See note)
0 : Last bit = “0 ”
1 : Last bit = “1 ”
Last receive bit (LRB)
(See note)
Note :
These bits and flags can be read out, but cannnot be written.
Indeterminate
R —
R —
R —
R —
R —
R W
0
R W
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