參數(shù)資料
型號(hào)： M37274MA-053SP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁(yè)數(shù)： 50/147頁(yè)
文件大?。?/td> 2042K
代理商： M37274MA-053SP
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50
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
Conditions for Setting Bit 4 of DSC3 to “1”
Data clock of 16 pulses has occured in sub-data slaice line
Data clock of 16 pulses has occured in sub-data slaice line
AND
Clock run-in pulse are detected 4 to 6 times
(10) 16-bit Shift Register
The caption data converted into a digital value by the comparator is
stored into the 16-bit shift register in synchronization with the data
clock. For the main data slice line, the contents of the high-order 8
bits of the stored caption data and the contents of the low-order 8
bits of the same data can be obtained by reading out data register 2
(address 00E5
16
) and data register 1 (address 00E4
16
), respectively.
For the sub-data slice line, the contents of the high-order 8 bits and
the contents of the low-order 8 bits can be obtained by reading out
the data register 4 (address 00ED
16
) and data register 3 (address
00EC
16
), respectively. These registers are reset to “0” at a falling of
V
sep
. Read out data registers 1 and 2 after the occurence of a data
slicer interrupt (refer to (11) Interrupt Request Generating Circuit).
(11) Interrupt Request Generating Circuit
The interrupt requests as shown in Table 6 are generated by
combination of the following bits; bits 5 and 6 of the clock run-in register
3 (address 0209
16
), bit 1 of the clock run-in register 2 (address
00E7
16
). Read out the contents of data registers 1 to 4 and the
contents of bits 3 to 7 of clock run-in detect registers 1 and 3 after the
occurence of a data slicer interrupt request.
Table 5. Setting Conditions for Caption Data Latch Completion Flag
Bit 7 of SP
0
1
Conditions for Setting Bit 7 of DSC1 to “1”
Data clock of 16 pulses has occured in main data slaice line
Data clock of 16 pulses has occured in main data slaice line
AND
Clock run-in pulse are detected 4 to 6 times
Slice line
Main data slice line
Sub-data slice line
b5
0
1
Sources
At end of data slice line
Data clock of 16 pulses has occured
AND
Clock run-in pulse are detected 4 to 6 times
Data clock of 16 pulses has occured
At end of data slice line
Data clock of 16 pulses has occured
AND
Clock run-in pulse are detected 4 to 6 times
Data clock of 16 pulses has occured
b6
0
1
0
1
CR2
b1
0
1
0
1
0
1
0
1
CR3
Table 6. Occurence Sources of Interrupt Request
Occurence Souces of Interrupt Request
(9) Data clock generating circuit
This circuit generates a data clock synchronized with the start bit
detected in the start bit detecting circuit.
Set the time from detection of the start bit to occurrence of the data
clock in bits 3 to 7 of clock run-in detect register 2 (address 00E9
16
).
The time to be set is represented by the following expression:
Time = (13 + set value)
reference clock period
For a data clock, 16 pulses are generated. When just 16 pulses have
been generated, bit 7 of the data slicer control register is set to “1”
(refer to Figure 32 to 34). When method 1 is already selected as a
start bit detecting method, this bit becomes a logical product (AND)
value with a clock run-in determination result by setting bit 7 of the
start bit position register to “1.”
When method 2 is already selected as a start bit detecting method
and 16 pulses are generated of a data clock regardless of bit 7 of the
start bit position register, this bit is set to “1.” The contents of this bit
are reset at a falling of the vertical synchronizing signal (V
sep
).
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