參數(shù)資料
型號： M37274MA-053SP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 14/147頁
文件大小： 2042K
代理商： M37274MA-053SP
14
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
Fig. 7. Memory Map of Special Function Register 2 (SFR2) (1)
210
16
211
16
212
16
213
16
214
16
215
16
216
16
217
16
218
16
219
16
21A
16
21B
16
21C
16
21D
16
21E
16
21F
16
200
16
201
16
202
16
203
16
204
16
205
16
206
16
207
16
208
16
209
16
20A
16
PWM mode register 1 (PN)
PWM mode register 2 (PW)
20B
16
20C
16
20D
16
20E
16
20F
16
Timer 5 (TM5)
Timer 6 (TM6)
Sync pulse counter register (SYC)
Data slicer control register 3 (DSC3)
PWM2 register (PWM2)
PWM3 register (PWM3)
PWM6 register (PWM6)
PWM4 register (PWM4)
PWM5 register (PWM5)
PWM0 register (PWM0)
PWM1 register (PWM1)
Interrupt input polarity register (IP)
Serial I/O mode register (SM)
Serial I/O register (SIO)
Clock source control register (CS)
I/O polarity control register (PC)
Extra font color register (EC)
Window H register 1 (WH1)
Window L register 1 (WL1)
Window H register 2 (WH2)
Window L register 2 (WL2)
Clock run-in detect register 3 (CRD3)
Clock run-in register (CR3)
Border color register (FC)
Raster color register (RC)
I
SFR2 area (addresses 200
16
to 21F
16
)
Address
Register
Bit allocation
State immediately after reset
: Fix to this bit to “0”
(do not write to “1”)
:
<
Bit allocation
>
<
State immediately after reset
>
: “0” immediately after reset
0
Function bit
:
No function bit
: Fix to this bit to “1”
(do not write to “0”)
Name
:
: Indeterminate immediately
after reset
1
: “1” immediately after reset
1
0
b7
b0 b7
b0
SYC0
FC2
00
16
00
16
FF
16
00
16
00
16
00
16
00
16
00
16
PW0
PW1
PW2
PW3
PW4
PW5
PW6
PN3
SYC1
SYC2
SYC3
SYC4
SYC5
DSC30
DSC31
DSC32
DSC37
DSC35
RE3
POL
0
AD/INT3
SEL
0
INT3
RE1
SM1
RE2
SM2
RE3
SM3
RE5
SM5
PC0
RE1
PC1
RE2
PC2
RE3
0
0
0
0
PC4
0
0
0
0
RE5
PC5
AD/INT3
SEL
AD/INT3
SEL
PC6
RE1
RE2
RE3
RE5
CS0
CS4
CS6
RC0
RE1
RC1
RE2
RC2
RE5
RC5
RC6
EC1
0
RE2
EC2
0
RE5
FC0
FC1
WH20
WH21
WL20
WL21
0
1
0
0
0
0
0
0
00
16
DSC36
DSC34 DSC33
00
16
07
16
0
0
0
0
CRD31
CRD32
CRD33
CRD34
CRD35
PN0
PN1
PN2
EC0
0
00
16
00
16
00
16
CR36
CR35 CR34 CR33 CR32 CR31
CR30
WL17 WL16 WL15 WL14 WL13 WL12 WL21 WL20
INT2
POL
SM4
WH17 WH16 WH15 WH14 WH13 WH12 WH11 WH10
0
00
16
SM0
0
0
0
0
0
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