參數(shù)資料
型號： M368L2923BUM-LC4
元件分類： DRAM
英文描述： 128M X 64 DDR DRAM MODULE, 0.65 ns, DMA184
封裝： DIMM-184
文件頁數(shù)： 7/23頁
文件大?。?/td> 359K
代理商： M368L2923BUM-LC4
DDR SDRAM
Revision 1.1 November. 2004
256MB, 512MB, 1GB Unbuffered DIMM Pb-Free
AC Timing Parameters and Specifications
Parameter
Symbol
CC(DDR400@CL=3)
C4(DDR400@CL=3)
Unit
Note
Min
Max
Min
Max
Row cycle time
tRC
55
60
ns
Refresh row cycle time
tRFC
70
ns
Row active time
tRAS
40
70K
40
70K
ns
RAS to CAS delay
tRCD
15
18
ns
Row precharge time
tRP
15
18
ns
Row active to Row active delay
tRRD
10
ns
Write recovery time
tWR
15
ns
Internal write to read command delay
tWTR
2
tCK
Clock cycle time
CL=3.0
tCK
5105
10
ns
16
CL=2.5
6126
12
ns
Clock high level width
tCH
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
0.45
0.55
tCK
DQS-out access time from CK/CK
tDQSCK
-0.55
+0.55
-0.55
+0.55
ns
Output data access time from CK/CK
tAC
-0.65
+0.65
-0.65
+0.65
ns
Data strobe edge to ouput data edge
tDQSQ
-
0.4
-
0.4
ns
13
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.72
1.28
0.72
1.28
tCK
Write preamble setup time
tWPRES
0
ps
5
Write preamble
tWPRE
0.25
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
4
DQS falling edge to CK rising-setup time
tDSS
0.2
tCK
DQS falling edge from CK rising-hold time
tDSH
0.2
tCK
DQS-in high level width
tDQSH
0.35
tCK
DQS-in low level width
tDQSL
0.35
tCK
Address and Control Input setup time
tIS
0.6
ns
h,7~10
Address and Control Input hold time
tIH
0.6
ns
h,7~10
Data-out high impedence time from CK/CK
tHZ
-
tAC max
-
tAC max
ns
3
Data-out low impedence time from CK/CK
tLZ
tAC min
tAC max
tAC min
tAC max
ns
3
Mode register set cycle time
tMRD
2
tCK
DQ & DM setup time to DQS, slew rate 0.5V/ns
tDS
0.4
ns
i, j
DQ & DM hold time to DQS, slew rate 0.5V/ns
tDH
0.4
ns
i, j
DQ & DM input pulse width
tDIPW
1.75
ns
9
Control & Address input pulse width for each input
tIPW
2.2
ns
9
Refresh interval time
tREFI
7.8
us
6
Output DQS valid window
tQH
tHP
-tQHS
-
tHP
-tQHS
-ns
12
Clock half period
tHP
min
tCH/tCL
-
min
tCH/tCL
-
ns
11, 12
相關(guān)PDF資料
PDF描述
M368L2923DUN-CB3 DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb D-die with 64/72-bit Non ECC/ECC 66 TSOP-II with Pb-Free (RoHS compliant)
M368L2923DUN-CCC DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb D-die with 64/72-bit Non ECC/ECC 66 TSOP-II with Pb-Free (RoHS compliant)
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相關(guān)代理商/技術(shù)參數(shù)
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M368L2923BUM-LCC 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb B-die with 64/72-bit Non ECC/ECC 66 TSOP-II
M368L2923BUN-CB3 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb B-die with 64/72-bit Non ECC/ECC 66 TSOP-II
M368L2923BUN-LB3 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb B-die with 64/72-bit Non ECC/ECC 66 TSOP-II
M368L2923CUN-CLCC 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module
M368L2923DUN 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Product Guide
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