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SUMMARY OF PRECAUTIONS
Appendix 4
Appendix 4-16
Rev.1.10 REJ09B0123-0110 Apr.06.07
32192/32195/32196 Group Hardware Manual
Appendix 4.9 Notes on Multijunction Timers
Appendix 4.9.12 Notes on using TOU single-shot PWM output mode
The following describes precautions to be observed when using TOU single-shot PWM output mode.
If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable
bit, the latter has priority so that count is disabled.
If the counter is accessed for read at the cycle of underflow, the counter value is read out as H'FFFF but
changes to “reload register value -1” at the next count clock timing.
Updating of reload 0 and reload 1 during timer operation does not effect PWM waveform that is outputting at
present. Updating is reflected at the next PWM period after updating reload 0 register.
Because a 0% or 100% duty-cycle needs to be determined when reloading the counter, there is a one count
clock equivalent delay before F/F is inverted and an interrupt or DMA transfer request is generated. However,
startup requests to other timers are not delayed. For details, see Appendix 4.9.16, “0% or 100% Duty-Cycle
Wave Output during PWM Output and Single-shot PWM Output Modes.”
Appendix 4.9.13 Notes on using TOU delayed single-shot output mode
The following describes precautions to be observed when using TOU delayed single-shot output mode.
If the counter stops due to an underflow in the same clock period as the timer is enabled by external input,
the former has priority so that the counter stops.
If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable
bit, the latter has priority so that count is enabled.
If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable
bit, the latter has priority so that count is disabled.
If the counter is accessed for read at the cycle of underflow, the counter value is read as H'FF FFFF but
changes to “reload register value -1” at the next count clock timing.
Because the timer operates synchronously with the count clock, a count clock-dependent delay is included
before F/F output is inverted after the timer is enabled.
Appendix 4.9.14 Notes on using TOU single-shot output mode
The following describes precautions to be observed when using TOU single-shot output mode.
If the counter stops due to an underflow in the same clock period as the timer is enabled by external input,
the former has priority so that the counter stops.
If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable
bit, the latter has priority so that count is enabled.
If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable
bit, the latter has priority so that count is disabled.
Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is
generated before F/F output is inverted after writing the enable bit.