
23
ELECTRICAL CHARACTERISTICS
23-39
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
23.9 A.C. Characteristics (when VCCE = 5 V)
(17) NBD timing
Symbol
Parameter
Measurement
Rated Value
Unit
See Fig.
Condition
MIN
MAX
23.9.19
tc(NBDCLK)
NBDCLK Input Cycle Time
80
ns
[103]
tw(NBDCLKL)
NBDCLK Input "L" Pulse Width
35
ns
[104]
tsu(NBDD-NBDCLKH)
NBDD Input Setup Time
20
ns
[107]
before NBDCLK
th(NBDCLKH-NBDD)
NBDD Input Hold Time
5
ns
[108]
after NBDCLK
tsu(NBDSYNCL-NBDCLKH)
NBDSYNC# Input Setup Time
20
ns
[109]
before NBDCLK
th(NBDCLKH-NBDSYNCL)
NBDSYNC# Input Hold Time
CL=100pF
5
ns
[110]
after NBDCLK
td(NBDCLKH-NBDD)
NBDD Output Delay Time
CL=100pF
7
tc(NBDCLK)-20
ns
[105]
after NBDCLK
tpzx(NBDCLKH-NBDDZ)
NBDD Output Enable Time
CL=100pF
5
ns
[130]
after NBDCLK
tv(NBDCLKH-NBDD)
NBDD Output Valid Time
CL=100pF
5
ns
[106]
after NBDCLK
tpxz(NBDCLKH-NBDDZ)
NBDD Output Disable Time
CL=100pF
60
ns
[131]
after NBDCLK
tw(NBDEVNTL)
NBDEVNT# Output "L" Pulse Width
CL=100pF
30
ns
[111]
Figure 23.9.19 NBD Timing
[103] tc(NBDCLK)
[104] tw(NBDCLKL)
[106] tv(NBDCLKH-NBDD)
[110] th(NBDCLKH-NBDSYNCL)
[111] tw(NBDEVNTL)
[109] tsu(NBDSYNCL-NBDCLKH)
[107] tsu(NBDD-NBDCLKH)
[105] td(NBDCLKH-NBDD)
0.8VCCE
0.2VCCE
[108] th(NBDCLKH-NBDD)
0.8VCCE
0.2VCCE
0.8VCCE
0.2VCCE
0.8VCCE
0.2VCCE
0.8VCCE
0.2VCCE
0.8VCCE
[130] tpzx(NBDCLKH-NBDDZ)
[131] tpxz(NBDCLKH-NBDDZ)
NBDCLK
(input)
NBDD3-0
(output)
NBDSYNC#
(input)
NBDEVNT#
(output)
NBDD3-0
(input)
Timing
requirements
Switching
characteristics