12
12-23
Serial I/O
12.2 Serial I/O Related Registers
32176 Group User’s Manual (Rev.1.01)
12.2.8 SIO Baud Rate Registers
SIO0 Baud Rate Register (S0BAUR)
<Address: H'0080 0117>
SIO1 Baud Rate Register (S1BAUR)
<Address: H'0080 0127>
SIO2 Baud Rate Register (S2BAUR)
<Address: H'0080 0137>
SIO3 Baud Rate Register (S3BAUR)
<Address: H'0080 0147>
<Upon exiting reset: Undefined>
b
Bit Name
Function
R
W
8–15
BRG
Set a baud rate divide value
R
W
Baud rate divide value
(1) BRG (baud rate divide value) (Bits 8–15)
The SIO Baud Rate Registers are used to set a baud rate divide value, so that the baud rate count source
selected by SIO Mode Register is divided by (BRG set value + 1).
Because the BRG value initially is undefined, be sure to set the divide value before the serial I/O starts
operating. The value written to the BRG during transmit/receive operation takes effect in the next cycle after
the BRG counter has finished counting.
When using the internal clock (to output the SCLKO signal) in CSIO mode, the serial I/O divides the internal
BCLK using a clock divider and then divides the resulting clock by (BRG set value + 1) and further by 2,
thereby generating a transmit/receive shift clock.
When using an external clock in CSIO mode, the serial I/O does not use the BRG. (Transmit/receive opera-
tions are synchronized to the externally supplied clock.)
During UART mode, the serial I/O divides the internal BCLK using a clock divider and then divides the
resulting clock by (BRG set value + 1) and further by 16, thereby generating a transmit/receive shift clock.
When using SIO0 or SIO1 in UART mode, set the relevant port (P84 or P87) to function as an SCLKO pin, so
that a BRG output clock divided by 2 can be output from that SCLKO pin.
When using the internal clock (internally clocked CSIO mode), if f(BCLK) is selected as the BRG count
source, make sure the transfer rate does not exceed 2 Mbits/second during CSIO mode.
b8
9
10
11121314
b15
BRG
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