![](http://datasheet.mmic.net.cn/30000/M32176F3TFP_datasheet_2359466/M32176F3TFP_28.png)
1-14
1
OVERVIEW
32176 Group User’s Manual (Rev.1.01)
1.4 Pin Assignments
The pins directed for input go to a high-impedance state (Hi-z) when reset. The term “when reset” reffers to
the period when input on RESET# pin is held low (the device remains reset), as well as when the RESET# pin
is released back high (the device comes out of reset).
Table 1.4.1 Pin Assignments of the 32176 (1/4)
Port
Other than
port
Other than
port
1
P221/CRX0
P221
CRX0
-
Input
3
OSC-VSS
-
OSC-VSS
--
4XIN
-
XIN
-
Input
5XOUT
-
XOUT
-
Output
6EXCOSC-VCC
-
EXCOSC-VCC
--
7N.C.
---
-
Function
Pin
No.
Symbol
Type
-
Input/output
-
Input/output
2
P225/A12
8
P30/A15
P30
A15
P225
A12
9
P31/A16
P31
A16
-
Input/output
10
P32/A17
P32
A17
-
Input/output
-
Input/output
-
Input/output
11
P33/A18
12
P34/A19
P34
A19
P33
A18
13
P35/A20
P35
A20
-
Input/output
14
P36/A21
P36
A21
-
Input/output
-
Input/output
15
P37/A22
P37
A22
Pin State When Reset
Function
Type
State during
reset
State upon
exiting reset
P221
Input
Hi-z
During single-chip mode
P225
Input
Hi-z
During external extension and
processor modes
A12
Output
Hi-z
Undefined
OSC-VSS
---
XIN
Input
--
XOUT
Output
XOUT
EXCOSC-VCC
---
----
During single-chip mode
P30
Input
Hi-z
During external extension and
processor modes
A15
Output
Hi-z
Undefined
During single-chip mode
P31
Input
Hi-z
During external extension and
processor modes
A16
Output
Hi-z
Undefined
During single-chip mode
P32
Input
Hi-z
During external extension and
processor modes
A17
Output
Hi-z
Undefined
During single-chip mode
P33
Input
Hi-z
During external extension and
processor modes
A18
Output
Hi-z
Undefined
During single-chip mode
P34
Input
Hi-z
During external extension and
processor modes
A19
Output
Hi-z
Undefined
During single-chip mode
P35
Input
Hi-z
During external extension and
processor modes
A20
Output
Hi-z
Undefined
During single-chip mode
P36
Input
Hi-z
During external extension and
processor modes
A21
Output
Hi-z
Undefined
During single-chip mode
P37
Input
Hi-z
During external extension and
processor modes
A22
Output
Hi-z
Undefined
Condition
20
VCCE
-
VCCE
--
21
VSS
-
VSS
--
-
Input/output
16
P20/A23
P20
A23
17
P21/A24
P21
A24
-
Input/output
18
P22/A25
P22
A25
-
Input/output
-
Input/output
-
Input/output
19
P23/A26
22
P24/A27
P24
A27
P23
A26
23
P25/A28
P25
A28
-
Input/output
24
P26/A29
P26
A29
-
Input/output
-
Input/output
-
Input/output
25
P27/A30
26
P00/DB0
P00
DB0
P27
A30
During single-chip mode
P20
Input
Hi-z
During external extension and
processor modes
A23
Output
Hi-z
Undefined
During single-chip mode
P21
Input
Hi-z
During external extension and
processor modes
A24
Output
Hi-z
Undefined
During single-chip mode
P22
Input
Hi-z
During external extension and
processor modes
A25
Output
Hi-z
Undefined
During single-chip mode
P23
Input
Hi-z
During external extension and
processor modes
A26
Output
Hi-z
Undefined
VCCE
---
VSS
---
During single-chip mode
P24
Input
Hi-z
During external extension and
processor modes
A27
Output
Hi-z
Undefined
During single-chip mode
P25
Input
Hi-z
During external extension and
processor modes
A28
Output
Hi-z
Undefined
During single-chip mode
P26
Input
Hi-z
During external extension and
processor modes
A29
Output
Hi-z
Undefined
During single-chip mode
P27
Input
Hi-z
During external extension and
processor modes
A30
Output
Hi-z
Undefined
During single-chip mode
P00
Input
Hi-z
During external extension and
processor modes
DB0
Input/output
Hi-z