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11
11-3
A-D Converter
32176 Group User’s Manual (Rev.1.01)
11.1 Outline of A-D Converter
(8) Interrupt Request and DMA Transfer Request Generation Functions
An A-D conversion interrupt or DMA transfer request can be generated each time A-D conversion or comparate
operation in single mode is completed, as well as when a single-shot scan operation or one cycle of continuous
scan operation is completed.
Note 1: To discriminate between the comparison performed internally by the successive approximation-
type A-D Converter and that performed in comparator mode using the same A-D Converter as a
comparator, the comparison in comparator mode is referred to in this manual as “comparate.”
Table 11.1.1 outlines the A-D Converter and Figure 11.1.1 shows block diagram of A-D Converter.
Table 11.1.1 Outline of the A-D Converter
Item
Description
Analog input
16 channels
A-D conversion method Successive approximation method
Resolution
10 bits (Conversion result can be read out in either 8 or 10 bits)
Absolute accuracy (Note 1)When sample-and-hold disabled
Slow mode
Normal speed
±2LSB
Conditions: Ta = 25°C,
or normal sample-and-hold enabled
Double speed
±2LSB
AVCC0 = 5.12 V,
Fast mode
Normal speed
±3LSB
VREF0 = 5.12 V
Double speed
±3LSB
When fast sample-and-hold enabled
Slow mode
Normal speed
±3LSB
Double speed
±3LSB
Fast mode
Normal speed
±3LSB
Double speed
±8LSB
Conversion mode
A-D conversion mode and comparator mode
Operation mode
Single mode, single-shot scan mode and continuous scan mode
Conversion start trigger Software start
Started by setting the A-D conversion start bit to "1"
Hardware start
A-D0 Converter
MJT (input event bus 2), MJT (input event bus 3),
MJT (output event bus 3) and MJT (TIN23S)
Conversion speed
During single mode
Slow mode
Normal speed 299BCLK
14.95s (Note 2)
BCLK:
( When sample-and-hold disabled
Double speed 173BCLK
8.65s
Internal peripheral clock When normal sample-and-hold enabled) Fast mode
Normal speed 131BCLK
6.55s
Double speed
89BCLK
4.45s
During single mode
Slow mode
Normal speed 191BCLK
9.55s
(When fast sample-and-hold enabled)
Double speed 101BCLK
5.05s
Fast mode
Normal speed
95BCLK
4.75s
Double speed
53BCLK
2.65s
During comparator mode
Slow mode
Normal speed
47BCLK
2.35s
Double speed
29BCLK
1.45s
Fast mode
Normal speed
23BCLK
1.15s
Double speed
17BCLK
0.85s
Sample-and-hold function Sample-and-hold function can be enabled or disabled as necessary.
A-D disconnection
Influences of the analog input voltage leakage from any preceding channel during scan
detection assist function mode operation are suppressed.
Interrupt request
Generated when A-D conversion or comparate operation is completed
generation function
Generated when a single-shot scan operation or one cycle of continuous scan operation is completed
DMA transfer request
Generated when A-D conversion or comparate operation is completed
generation function
Generated when a single-shot scan operation or one cycle of continuous scan operation is completed
Note 1: The conversion accuracy stipulated here refers to that of the microcomputer alone, with influences of the power
supply wiring and noise on the board not taken into account.
Note 2: This indicates the conversion time when f(BCLK) = 20 MHz (1 BCLK = 50 ns).