
12
12-56
Rev.1.0
SERIAL I/O
12.6 Transmit Operation in UART Mode
Figure 12.6.5 Example of UART Transmission (Transmitted Only Once, with Transmit Interrupt Used)
12.6.9 Typical UART Transmit Operation
The following shows a typical transmit operation in CSIO mode.
Note 1 : Change of the Interrupt Controller "SIO Transmit Interrupt Control Register" interrupt request bit
Note 2 : When transmit-finished interrupt is enabled (DMA transfer can also be requested at the same
timing)
Note 3 : The Interrupt Controller IVECT register is read or "SIO Transmit Interrupt Control Register" interrupt
request bit cleared
Note 4 : Transmit interrupt request is generated when transmission is enabled.
Note 5 : Even after transmit data is written to the transmit buffer, a transmit interrupt request is generated
when the data is transferred from the transmit buffer to the transmit shift register and the transmit
buffer is thereby emptied.
: Processing by software
: Interrupt generation
<UART on receive side>
TXD
RXD
Set
Write to
transmit
buffer register
Transmit buffer
empty bit
Transmit enable bit
Cleared
Transmit status bit
ST
D7
D6
D0 PAR ST
ST
TXD
SIO transmit interrupt
(Note 1)
Transmit
interrupt
(Note 4)
Interrupt request accepted
Transferred from transmit
buffer to transmit shift register
(transmission starts)
(Note 2)
(Note 3)
<UART on transmit side>
Transmit
interrupt
(Note 5)
Cleared