12
12-17
Rev.1.0
s SIO47 Receive Interrupt Cause Select Register (SI47SEL)
<Address: H'0080 0A02>
<When reset: H'00>
D
Bit Name
Function
R
W
0-3
No functions assigned
0
–
4
ISR4
0: Receive complete interrupt
(SIO4 receive interrupt cause select bit)
1: Receive error interrupt
5
ISR5
0: Receive complete interrupt
(SIO5 receive interrupt cause select bit)
1: Receive error interrupt
6
ISR6
0: Receive complete interrupt
(SIO6 receive interrupt cause select bit)
1: Receive error interrupt
7
ISR7
0: Receive complete interrupt
(SIO7 receive interrupt cause select bit)
1: Receive error interrupt
This register selects the cause of interrupt generated at completion of receive operation.
[When set to 0]
Setting this bit to 0 selects Receive complete interrupt (receive buffer full). A receive
complete interrupt is generated even when an error occurred when receiving data
(except for an overrun error).
[When set to 1]
Setting this bit to 1 selects Receive error interrupt. Following are detected for receive
errors:
CSIO mode : Overrun error
UART mode : Overrun, parity, and framing errors
D0
123
456
D7
ISR4
ISR5
ISR6
ISR7
SERIAL I/O
12.2 Serial I/O Related Registers
