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參數(shù)資料
| 型號： | M32000D3FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片32位CMOS微機 |
| 文件頁數(shù)： | 28/45頁 |
| 文件大小： | 565K |
| 代理商： | M32000D3FP |
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D3FP
28
Programmable I/O port
The M32000D3FP has two programmable I/O ports (PP0, PP1). Each
port can be set as input or output.
Reset
When an "L" level is input to RST, the M32000D3FP switches to the
____
reset interrupt. All internal resources including the internal PLL (4x
clock generator) are initialized. In order to stabilize PLL oscillation,
the "L" input to RST should last a minimum of 2 ms after VCC stabi-
lizes to the specified voltage level.
<at reset: H'00>
R
0
D
24 - 30
31
bit name
Not assigned.
PP0C, PP1C
(port I/O direction)
function
W
0: input port
1: output port
programmable I/O port direction control register 1 (PPCR1)
< address: H'FFFF FFE7>
D24
D25
D26
D27
D28
D29
D30
D31
PP1C
programmable I/O port direction control register 0 (PPCR0)
< address: H'FFFF FFE3>
D24
D25
D26
D27
D28
D29
D30
D31
PP0C
Fig. 30 Programmable I/O port direction control register
programmable I/O port data register 0 (PPDR0)
< address: H'FFFF FFEB>
<at reset: B'0000 000>
function
D
24 - 30
31
bit name
Not assigned.
PP0D, PP1D
(port data)
R
0
W
0: data = "0"
1: data = "1"
D24
D25
D26
D27
D28
D29
D30
D31
PP1D
programmable I/O port data register 1 (PPDR1)
< address: H'FFFF FFEF>
D24
D25
D26
D27
D28
D29
D30
D31
PP0D
Fig. 31 Programmable I/O port data register
Table 2 Internal state after reset
internal resources
DRAM
cache memory
state
undefined
invalid
(purged all)
undefined
general purpose
registers
(R0 - R15)
control registers PSW (CR0)
B'0000 0000 0000 0000 00 000 0000 0000
(BSM, BIE, and BC are undefined)
H'0000 0000
undefined
undefined
undefined
CBR (CR1)
SPI (CR2)
SPU (CR3)
BPC (CR6)
PC
master mode:
execute from address H'7FFF FFF0
slave mode:
wait for interrupt input at address
H'7FFF FFF0
execute from address H'0000 0010
by inputting SBI signal
execute from address H'0000 0080
by inputting INT signal
ACC
(accumulator)
PPCR0, PPCR1
H'00 (input)
PPDR0, PPDR1
B'0000 000 (depends on input
pin state)
MLCR
H'00 (HREQ exclusive lock mode)
MPMR
H'00 (normal operation)
MCCR
H'01 (cache-off mode)
undefined
I/O registers
R = 0 ... "0" when reading
W =
... write enabled
R =
W =
... read enabled
: write disabled
R = 0 ... "0" when reading
W =
... write enabled
R =
W =
... read enabled
: write disabled
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