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| 型號： | M32000D3FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片32位CMOS微機 |
| 文件頁數(shù)： | 20/45頁 |
| 文件大小： | 565K |
| 代理商： | M32000D3FP |
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D3FP
20
Read and write operations of the M32000D3FP are carried out using
the address bus, data bus, and the R/W, BCH, BCL and DC signals.
_______
BCL signals go to an "L" level. The CPU reads the data in the valid
byte positions. When writing, an "L" level is output from R/W, and
BCH and BCL are output according to the valid byte positions, so as
to specify the byte positions for writing into an external device.
Keep DC signal at the "H" level during idle cycles.
idle
read
"H"
"H"
CLKIN
BS
A8 - A30
SID, ST
BCH, BCL
BURST
D0 - D15
DC
R/W
idle
read
idle
write
idle
write
CLKIN
BS
A8 - A30
SID, ST
BCH, BCL
BURST
D0 - D15
DC
R/W
"H"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
Note:
"Hi-z" means high-impedance, and indicates sampling timing.
Fig. 16 Read/write timing (two no-wait accesses)
Internal DRAM access control (CS)
The internal DRAM can be accessed when CS is driven to an "L"
level after the M32000D3FP enters the hold state (HACK = "L").
To access the internal DRAM from external, the following signals
from the system bus side should be controlled.
A8 to A30
Input internal DRAM addresses to be read or written.
BCH, BCL
Specify the byte position of data to be written into the internal
DRAM. BCH corresponds to the MSB side (D0 to D7), and BCL
corresponds to the LSB side (D8 to D15).
R/W
Specify read or write operation. When reading, R/W = "H". When
writing, R/W = "L".
D0 to D15
16-bit data I/O bus.
SID
When accessing the internal DRAM from an external bus mas-
ter, an "L" level is input to SID to specify user space.
DC
This signal notifies to an external bus master that the internal
DRAM access is complete. When access is complete, an "L"
level is output to DC.
Table 1 Pin condition in hold state
pin name
BCH, BCL
ST, R/W, BS, BURST
D0 - D15
pin condition or operation
high-impedance
output when internal DRAM is read
by an external bus master (CS = "L",
R/W = "H"), otherwise high-impedance
output when internal DRAM is
accessed by an external bus master
__
(CS = "L"), otherwise high-impedance
output "L"
normal operation
DC
HACK
other pins
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