參數(shù)資料
型號： M30876MJA-XXXFP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 32 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 61/93頁
文件大?。?/td> 2401K
代理商： M30876MJA-XXXFP
5. Electrical Characteristics
Page 62 of 85
Switching Characteristics
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85
°C unless otherwise specified)
Table 5.29
Memory Expansion Mode and Microprocessor Mode (when accessing external
memory space)
NOTES:
1. Values, which depend on BCLK frequency, can be obtained from the following equations.
109
f(BCLK) × 2
- 15 [ns]
th(WR-DB) =
109
f(BCLK) × 2
- 10 [ns]
th(WR-AD) =
109
f(BCLK) × 2
- 10 [ns]
th(WR-CS) =
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following
equations.
109 × n
f(BCLK) × 2
- 15 [ns] (if external bus cycle is a
φ + bφ, n = (b × 2) - 1)
tw(WR)
=
109 × m
f(BCLK)
- 20 [ns] (if external bus cycle is a
φ + bφ, m = b)
td(DB-WR) =
3. tc [ns] is added when recovery cycle is inserted.
Symbol
Parameter
Measurement
Condition
Standard
Unit
Min.
Max.
td(BCLK-AD)
Address output delay time
18
ns
th(BCLK-AD)
Address output hold time (BCLK standard)
-3
ns
th(RD-AD)
Address output hold time (RD standard)(3)
0
ns
th(WR-AD)
Address output hold time (WR standard)(3)
(note 1)
ns
td(BCLK-CS)
Chip-select signal output delay time
18
ns
th(BCLK-CS)
Chip-select signal output hold time (BCLK standard)
-3
ns
th(RD-CS)
Chip-select signal output hold time (RD standard)(3)
0
ns
th(WR-CS)
Chip-select signal output hold time (WR standard)(3)
(note 1)
ns
td(BCLK-RD)
RD signal output delay time
18
ns
th(BCLK-RD)
RD signal output hold time
-5
ns
td(BCLK-WR)
WR signal output delay time
18
ns
th(BCLK-WR)
WR signal output hold time
-5
ns
td(DB-WR)
Data output delay time (WR standard)
(note 2)
ns
th(WR-DB)
Data output hold time (WR standard)(3)
(note 1)
ns
tw(WR)
WR output width
(note 2)
ns
VCC1 = VCC2 = 5V
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相關(guān)代理商/技術(shù)參數(shù)
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