參數(shù)資料
型號： M30876MJA-XXXFP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 32 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 60/93頁
文件大?。?/td> 2401K
代理商： M30876MJA-XXXFP
5. Electrical Characteristics
Page 61 of 85
Timing Requirements
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85
°C unless otherwise specified)
Table 5.28
Memory Expansion mode and Microprocessor Mode
NOTE:
1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following
equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative.
109 × m
f(BCLK) × 2
- 35 [ns] (if external bus cycle is a
φ + bφ, m = (b × 2) + 1)
tac1(RD-DB) =
109 × n
f(BCLK)
- 35 [ns] (if external bus cycle is a
φ + bφ, n = a + b)
tac1(AD-DB) =
109 × m
f(BCLK) × 2
- 35 [ns] (if external bus cycle is a
φ + bφ, m = (b × 2) - 1)
tac2(RD-DB) =
109 × p
f(BCLK) × 2
- 35 [ns] (if external bus cycle is a
φ + bφ, p = {(a + b - 1) × 2} + 1)
tac2(AD-DB) =
Symbol
Parameter
Standard
Unit
Min.
Max.
tac1(RD-DB)
Data input access time (RD standard)
(note 1)
ns
tac1(AD-DB)
Data input access time (AD standard, CS standard)
(note 1)
ns
tac2(RD-DB)
Data input access time (RD standard, when accessing a space with the
multiplexed bus)
(note 1)
ns
tac2(AD-DB)
Data input access time (AD standard, when accessing a space with the
multiplexed bus)
(note 1)
ns
tsu(DB-BCLK)
Data input setup time
26
ns
tsu(RDY-BCLK)
RDY input setup time
26
ns
tsu(HOLD-BCLK) HOLD input setup time
30
ns
th(RD-DB)
Data input hold time
0
ns
th(BCLK-RDY)
RDY input hold time
0
ns
th(BCLK-HOLD)
HOLD input hold time
0
ns
td(BCLK-HLDA)
HLDA output delay time
25
ns
VCC1 = VCC2 = 5V
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M30876MJA-XXXGP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU
M30876MJB-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU
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M30876MJ-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU
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