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Interrupts
89
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Under
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
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INT Interrupt
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INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the
IFSR register's IFSRi bit.
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INT4 and INT5 share the interrupt vector and interrupt control register with SI/O3 and SI/O4, respectively.
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To use the INT4 interrupt, set the IFSR register’s IFSR6 bit to “1” (= INT4). To use the INT5 interrupt, set the
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IFSR register’s IFSR7 bit to “1” (= INT5).
After modifying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to “0” (= interrupt not requested)
before enabling the interrupt.
Figure 1.11.10 shows the IFSR and IFSR2A registers.
Figure 1.11.10. IFSR Register and IFSR2A Register
Interrupt request cause select register
Bit name
Function
Bit symbol
RW
Symbol
Address
After reset
IFSR
035F16
0016
IFSR0
b7
b6
b5
b4
b3
b2
b1
b0
INT0 interrupt polarity
switching bit
0 : SI/O3
1 : INT4
0 : SI/O4
1 : INT5
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
INT1 interrupt polarity
switching bit
INT2 interrupt polarity
switching bit
INT3 interrupt polarity
switching bit
INT4 interrupt polarity
switching bit
INT5 interrupt polarity
switching bit
0 : One edge
1 : Both edges
Interrupt request cause
select bit
Interrupt request cause
select bit
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
IFSR6
IFSR7
RW
(Note 1)
(Note 3)
(Note 2)
Note 1: When setting this bit to “1” (= both edges), make sure the INT0IC to INT5IC register’s POL bit
is set to “0” (= falling edge).
Note 2: During memory expansion and microprocessor modes, set this bit to “0” (= SI/O3, SI/O4)
Note 3: When setting this bit to “0” (= SI/O3, SI/O4), make sure the S3IC and S4IC registers’ POL bit is
set to “0” (= falling edge).
Interrupt request cause select register 2
Bit name
Function
Bit symbol
RW
Symbol
Address
After reset
IFSR2A
035E16
00XXXXXX2
b7
b6
b5
b4
b3
b2
b1
b0
0 : Timer B3
1 : UART0 bus collision
detection
0 : Timer B4
1 : UART1 bus collision
detection
IFSR26
IFSR27
Interrupt request cause
select bit
Interrupt request cause
select bit
RW
(b5-b0)
Nothing is assigned. When write, set to “0”.
When read, their contents are indeterminate.