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| 型號(hào)： | M30600E8GP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 72/139頁(yè) |
| 文件大?。?/td> | 1782K |
| 代理商： | M30600E8GP |
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Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
38
Interrupts
Tables 1.16 and 1.17 show the interrupt sources and vector addresses. When an interrupt is received, the
program is executed from the address shown by the respective interrupt vector.
The vector addresses for the interrupts in Table 1.16 are fixed (interrupt vector addresses). These inter-
rupts are not affected by the interrupt enable flag (I flag) (non-maskable interrupts).
The vector table addresses for the interrupt in Table 1.17 are variable, being determined as relative to the
fixed address in the interrupt table register (INTB) (variable interrupt addresses). These interrupts can be
enabled or disabled using the interrupt enable flag (I flag) (maskable interrupts). 64 vectors can be set in
the interrupt table register (INTB). Any software interrupt Nos. 0 to 63 can be assigned to each vector. By
using the INT instruction to specify a software interrupt No., the program can be executed starting at the
address indicated by the respective vector. The BRK instruction interrupt has interrupt vectors in both the
fixed vector addresses and variable vector addresses. When the contents of FFFE416 to FFFE716 are all
“FF16”, the program is executed from the address shown in the BRK instruction interrupt vector in the
variable vector addresses.
Specify the starting address of the interrupt program in the interrupt vector. Figure 1.25 shows the format
for specifying the address.
Interrupt source
Vector table addresses
Remarks
Address (L) to address (H)
Undefined instruction
FFFDC16 to FFFDF16
Interrupt on UND instruction
Overflow
FFFE016 to FFFE316
Interrupt on INTO instruction
BRK instruction
FFFE416 to FFFE716
If the vector is filled with FF16, program execution starts from
the address shown by the vector in the variable vector table
Address match
FFFE816 to FFFEB16
There is an address-matching interrupt enable bit
Single step (Note)
FFFEC16 to FFFEF16
Do not use
Watchdog timer
FFFF016 to FFFF316
________
DBC (Note)
FFFF416 to FFFF716
Do not use
_______
NMI
FFFF816 to FFFFB16
_______
External interrupt by input to NMI pin
Reset
FFFFC16 to FFFFF16
Table 1.16. Interrupt factors (fixed interrupt vector addresses)
Figure 1.25. Format for specifying interrupt vector addresses
Mid address
Low address
0 0 0 0
High address
0 0 0 0
Vector address + 0
Vector address + 1
Vector address + 2
V
ector address + 3
LSB
MSB
Note: Interrupts used for debugging purposes only.
Interrupts
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相關(guān)代理商/技術(shù)參數(shù) |
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