參數(shù)資料
型號(hào)： M30600E8GP
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 70/139頁(yè)
文件大小： 1782K
代理商： M30600E8GP
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Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
36
CM17
CM16
CM07
CM06
CM05
CM04
Operating mode of internal clock
0
1
0
Invalid
Division by 2 mode
1
0
Invalid
Division by 4 mode
Invalid
0
1
0
Invalid
Division by 8 mode
1
0
Invalid
Division by 16 mode
0
Invalid
No-division mode
Invalid
1
Invalid
0
1
Low-speed mode
Invalid
1
Invalid
1
Low power dissipation mode
Status Transition Of Internal Clock
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
internal clock
. Table 1.15 shows the operating modes corresponding to the settings of system clock
control registers 0 and 1.
After a reset, operation defaults to division by 8 mode. When shifting to stop mode, the main clock division select
bit 0 (bit 6 at address 000616) is set to “1”. The following shows the operational modes of internal clock
:
(1) Division by 2 mode
The main clock is divided by 2 to obtain the internal clock
.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the internal clock
.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the internal clock
. Note that oscillation of the main clock must
have stabilized before transferring from this mode to another mode.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the internal clock
.
(5) No-division mode
The main clock is used as internal clock
.
(6) Low-speed mode
fC is used as internal clock
. Note that oscillation of both the main and sub clocks must have stabilized
before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the
sub clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the internal clock
and the main clock is stopped.
Table 1.15. Operating modes dictated by settings of system clock control registers 0 and 1
Status Transition Of Internal Clock
相關(guān)PDF資料
PDF描述
M30600M8-XXXGP 16-BIT, MROM, MICROCONTROLLER, PQFP100
M30610MCA-XXXGP 16-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP100
M30610ECFS 16-BIT, UVPROM, 10 MHz, MICROCONTROLLER, CQCC100
M30612M4A-XXXGP 16-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP100
M30610ECGP 16-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
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