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參數(shù)資料
| 型號(hào)： | M30600E8GP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 66/139頁(yè) |
| 文件大?。?/td> | 1782K |
| 代理商： | M30600E8GP |
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Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
32
The following paragraphs describe the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the internal clock
. The clock can be stopped using the main clock stop bit (bit 5 at address 000616).
Stopping the clock reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the XOUT pin
can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive
capacity of the XOUT pin reduces the power dissipation. This bit defaults to “1” when shifting to stop mode
and after a reset.
(2) Sub clock
The sub clock is generated by the sub clock oscillation circuit. No sub clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub clock can be
selected as the internal clock
by using the system clock select bit (bit 7 at address 000616). However,
be sure that the sub clock oscillation has fully stabilized before switching.
After the oscillation of the sub clock oscillation circuit has stabilized, the drive capacity of the XCOUT pin
can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the
drive capacity of the XCOUT pin reduces the power dissipation. This bit changes to “1” when shifting to
stop mode and at a reset.
(3) Internal clock
The internal clock
is the clock that drives the CPU, and is either the main clock or fc or is derived by
dividing the main clock by 2, 4, 8, or 16. The internal clock
is derived by dividing the main clock by 8
after a reset.
When shiffing to stop mode, the main clock division select bit (bit 6 at 000616) is set to “1”.
(4) Peripheral function clock
f1, f8, f32
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
fAD
This clock has the same frequency as the main clock and is used for A-D conversion.
(5) fC32
This clock is derived by dividing the sub clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub clock. It is used for internal clock
and for the watchdog
timer.
Clock Generating Circuit
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