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| 型號(hào)： | M30600E8GP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 57/139頁(yè) |
| 文件大?。?/td> | 1782K |
| 代理商： | M30600E8GP |
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Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
24
Bus Control
The following explains the signals required for accessing external devices and software waits. The signals
required for accessing the external devices are valid when the processor mode is set to memory expansion
mode and microprocessor mode. The software waits are valid in all processor modes.
(1) Address bus/data bus
The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space.
The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function
as the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus.
Both the address and data bus retain their previous states when internal ROM or RAM is accessed.
Also, when a change is made from single-chip mode to memory expansion mode, the value of the
address bus is undefined until external memory is accessed.
(2) Chip select signal
The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control
register (address 000816) set each pin to function as a port or to output the chip select signal. The chip
select control register is valid in memory expansion mode and microprocessor mode. In single-chip
mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control
register.
_______
In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been can-
_______
celled. CS1 to CS3 function as input ports. Therefore, when using CS1 to CS3, external pull-up resis-
tors are required. Figure 1.16 shows the configuration of the chip select control register.
The chip select signal can be used to split the external area into as many as four blocks. Table 1.6
shows the external memory areas specified using the chip select signal.
Figure 1.16. Configuration of chip select control register
Chip select control register
Symbol
Address
When reset
CSR
0008 16
01 16
Bit name
Function
W
R
b7
b6
b5
b4
b3
b2
b1
b0
CS1 output enable bit
CS1
CS0
CS3
CS2
CS0 output enable bit
CS2 output enable bit
CS3 output enable bit
CS1W
CS0W
CS3W
CS2W
CS0 wait bit
CS1 wait bit
CS2 wait bit
CS3 wait bit
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
0 : Wait state inserted
1 : No wait state
Bit symbol
Bus Control
Chip select
Specified address range
Memory expansion mode
Microprocessor mode
_______
CS0
9000016 to CFFFF16(256K)
9000016 to FFFFF16
(448K)
_______
CS1
1000016 to 8FFFF16(512K)
1000016 to 8FFFF16
(512K)
_______
CS2
0800016 to 0FFFF16 (32K)
0800016 to 0FFFF16
(32K)
_______
CS3
0400016 to 07FFF16 (16K)
0400016 to 07FFF16
(16K)
Table 1.6. External areas specified by the chip select signals
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相關(guān)代理商/技術(shù)參數(shù) |
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