參數(shù)資料
型號(hào): M30201MX-XXXFP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機(jī)
文件頁數(shù): 38/159頁
文件大?。?/td> 1496K
代理商: M30201MX-XXXFP
Unde
Interrupts
deeopmen
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
38
Interrupt sources without priority levels
7
0
Value set in the IPL
Watchdog timer
Other
Not changed
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 1.12 is set in the IPL.
Table 1.12. Relationship between interrupts without interrupt priority levels and IPL
Table 1.11. Time required for executing the interrupt sequence
Stack pointer (SP) value
Interrupt vector address
Reset
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 1.11.
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
Figure 1.26. Time required for executing the interrupt sequence
16-bit bus, without wait
8-bit bus, without wait
Even
Even
Odd (Note 2)
Odd (Note 2)
Even
Odd
Even
Odd
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
Indeterminate
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Indeterminate
SP-2
contents
SP-4
contents
vec
contents
vec+2
contents
Interrupt
information
Address
0000
16
Indeterminate
SP-2
SP-4
vec
vec+2
PC
BCLK
Address bus
Data bus
W
R
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