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參數(shù)資料
| 型號： | M2V56S30ATP-6 |
| 元件分類： | DRAM |
| 英文描述： | 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 X 0.875 INCH, TSOP2-54 |
| 文件頁數(shù)： | 5/51頁 |
| 文件大?。?/td> | 430K |
| 代理商： | M2V56S30ATP-6 |
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13
MITSUBISHI ELECTRIC
May '02
MITSUBISHI LSIs
SDRAM (Rev.1.41)
Single Data Rate
M2V56S20/ 30/ 40 AKT
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP
Current State
CKE
n-1
CKE
n
/CS
/RAS /CAS
/WE
Add
Action
SELF-
REFRESH*1
H
X
INVALID
L
H
X
Exit Self-Refresh (Idle after tRFC)
L
H
L
H
X
Exit Self-Refresh (Idle after tRFC)
L
H
L
H
L
X
ILLEGAL
L
H
L
H
L
X
ILLEGAL
L
H
L
X
ILLEGAL
L
X
NOP (Maintain Self-Refresh)
POWER
DOWN
H
X
INVALID
L
H
X
Exit Power Down to Idle
L
X
NOP (Maintain Power Down)
ALL BANKS
IDLE*2
H
X
Refer to Function Truth Table
H
L
H
X
Enter Self-Refresh
H
L
H
X
Enter Power Down
H
L
H
X
Enter Power Down
H
L
H
L
X
ILLEGAL
H
L
H
L
X
ILLEGAL
H
L
X
ILLEGAL
L
X
Refer to Current State =Power Down
ANY STATE
other than
listed above
H
X
Refer to Function Truth Table
H
L
X
Begin CLK Suspend at Next Cycle*3
L
H
X
Exit CLK Suspend at Next Cycle*3
L
X
Maintain CLK Suspend
FUNCTION TRUTH TABLE for CKE
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously
A minimum setup time must be satisfied before any command other than EXIT.
2. Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M2V56S30ATP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30ATP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30TP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30TP-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30TP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
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