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參數(shù)資料
| 型號： | M2V56S30ATP-6 |
| 元件分類： | DRAM |
| 英文描述： | 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 X 0.875 INCH, TSOP2-54 |
| 文件頁數(shù)： | 1/51頁 |
| 文件大?。?/td> | 430K |
| 代理商： | M2V56S30ATP-6 |
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MITSUBISHI ELECTRIC
May '02
MITSUBISHI LSIs
SDRAM (Rev.1.41)
Single Data Rate
M2V56S20/ 30/ 40 AKT
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP
Contents are subject to change without notice.
DESCRIPTION
FEATURES
Standard
PC100 (CL2)
PC133 (CL3)
PC133 (CL2)
133MHz
100MHz
133MHz
M2V56S20/30/40ATP/KT-7/-7L/-7UL
M2V56S20/30/40ATP/KT-6/-6L/-6UL
M2V56S20/30/40ATP/KT-5/-5L/-5UL
Max. Frequency
@CL3
Max. Frequency
@CL2
M2V56S20ATP/ KT is a 4-bank x 16777216-word x 4-bit,
M2V56S30ATP/ KT is a 4-bank x 8388608-word x 8-bit,
M2V56S40ATP/ KT is a 4-bank x 4194304-word x 16-bit,
synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of
CLK. The M2V56S20/30/40A achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6),
and are suitable for main memory or graphic memory in computer systems.
- Single 3.3v + 0.3V power supply
- Max. Clock frequency -5:PC133<2-2-2> / -6:PC133<3-3-3> / -7:PC100<2-2-2>
- Fully Synchronous operation referenced to clock rising edge
- Single Data Rate
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/full page (programmable)
- Burst type- sequential / interleave (programmable)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- LVTTL Interface
- Both 54-pin TSOP Package and 64-pin Small TSOP Package
M2V56S*0ATP: 0.8mm lead pitch 54-pin TSOP Package
M2V56S*0AKT: 0.4mm lead pitch 64-pin Small TSOP Package (sTSOP)
-Low Power for the Self Refresh Current
Ultra Low Power Version : ICC6 < 1mA
( -5UL , -6UL , -7UL )
Low Power Version
: ICC6 < 2mA
( -5L , -6L
, -7L )
Note: The –5L/-6L/-7L is Self-refresh low power.
The –5UL/-6UL/-7UL is Self-refresh ultra low power.
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相關(guān)代理商/技術(shù)參數(shù) |
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| M2V56S30ATP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30ATP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30TP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30TP-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30TP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
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