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參數(shù)資料
| 型號(hào)： | M2V56S30ATP-6 |
| 元件分類： | DRAM |
| 英文描述： | 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 X 0.875 INCH, TSOP2-54 |
| 文件頁(yè)數(shù)： | 17/51頁(yè) |
| 文件大小： | 430K |
| 代理商： | M2V56S30ATP-6 |
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24
MITSUBISHI ELECTRIC
May '02
MITSUBISHI LSIs
SDRAM (Rev.1.41)
Single Data Rate
M2V56S20/ 30/ 40 AKT
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
DQM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Write recovery time (tWR) is
required from the last data to PRE command. During write recovery, data inputs must be masked by
DQM.
[ Write Interrupted by Burst Terminate ]
Burst terminate command can terminate burst write operation. In this case, the write recovery time is
not required and the bank remains active. WRITE to TBST interval is minimum 1 CLK.
Write
Ya
0
00
Write Interrupted by Precharge (BL=4)
ACT
Xa
0
00
Da0
Da1
PRE
0
00
ACT
Xa
0
00
Write
Ya
0
00
Write Interrupted by Burst Terminate (BL=4)
ACT
Xa
0
00
Da0
Da1
TBST
Write
Yb
0
00
Db0
Db1
Db2
Db3
tWR
tRP
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2V56S30ATP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30ATP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30TP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30TP-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30TP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
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