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參數(shù)資料
| 型號(hào)： | M. CORE |
| 廠商： | Motorola, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 高度集成，低功耗，32位微控制器 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 57K |
| 代理商： | M. CORE |
4
MCORE ARCHITECTURAL INFORMATION
MOTOROLA
expensive and smaller memories, decreasing overall system cost, while also using less memory on-chip for
more integrated solutions.
HARDWARE ACCELERATOR INTERFACE (HAI)
The MCORE engine provides support for task acceleration by external hardware blocks which are
optimized for specific application-related operations. Data is transferred between the core and an
Accelerator Block by one or more of several mechanisms as appropriate for a particular implementation.
These external hardware blocks may be as simple as a block for performing a population count, or a more
complicated function such as a DSP acceleration block capable of high speed multiply/accumulate
operation or data encryption.
DEBUG INTERFACE
The MCORE architecture supports on-chip emulation (OnCE) circuitry through the JTAG interface, which
provides a means of interacting with the MCORE processor core and any peripherals. This allows a user
to examine registers, memory, or on-chip peripherals facilitating hardware/software development on the
MCORE processor core. Internal Status and Control registers are accessible via the serial scan chain
during OnCE. To achieve this, special circuits and dedicated pins for the MCORE processor core are
provided to avoid sacrificing any user-accessible on-chip resources.
TARGET APPLICATIONS
The MCORE architecture represents a new level of performance for embedded applications -- an
innovative, ultra-low power microRISC core designed to power a new generation of portable and mobile
applications. Smaller in size and offering full 32-bit performance out of 16-bit memory, MCORE delivers a
high-performance, low-power solution ideally suited for battery-powered and wireless applications,
including digital phones, pagers, electronic personal assistants, and for automotive safety products like ABS
and Airbags, where system cost and high temperature rages are key variables. Combining performance and
cost efficiencies in a compact, low-power design, MCORE is the natural solution for any application where
battery life and system costs are as important as MIPS.
DEVELOPMENT TOOLS AND EVALUATION SYSTEMS
A solid selection of third-party development tools is available for the MCORE processor, including highly
optimized compilers, instruction-set simulators, debuggers, target monitors, software/hardware co-
verification tools, real-time operating systems and evaluation boards. The MCORE architecture is also
supported by an Application Binary Interface (ABI) Standard, that defines all the interfaces required by a
compiler writer to create a toolchain for MCORE. This standard allows interoperability between other ABI
compliant MCORE tools. To provide additional support and protection, MCORE development tools are
fully tested to ensure “customer-ready” validation before being released.
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