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參數(shù)資料
| 型號： | M. CORE |
| 廠商： | Motorola, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 高度集成，低功耗，32位微控制器 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 57K |
| 代理商： | M. CORE |
2
MCORE ARCHITECTURAL INFORMATION
MOTOROLA
On-Chip Emulation Support
Full Static Design for Minimizing Power Consumption
Fully Supported by Industry-Leading Third-Party Development Tools
OVERVIEW
Figure 1 is a block diagram of the MCORE processor. The following paragraphs provide an overview of the
MCORE processor.
Figure 1. MCORE Block Diagram
MCORE PROCESSOR CORE
The MCORE utilizes a four-stage pipeline for instruction execution. The Instruction Fetch, Instruction Decode/
Register File Read, Execute, and Register File Writeback stages operate in an overlapped fashion, allowing
single clock instruction execution for most instructions.
Sixteen general purpose registers are provided for source operands and instruction results. Register R15 is
used as the Link Register to hold the return address for subroutine calls and Register R0 is used as the current
Stack Pointer by convention.
The execution unit consists of a 32-bit Arithmetic/Logic Unit (ALU), a 32-bit Barrel Shifter (Shifter), Find-First-
One unit (FFO), Result Feed-Forward hardware, and miscellaneous support hardware for multiplication,
division, and multiple register load and stores. Arithmetic and Logical operations are executed in a single cycle
with the exception of multiply and divide. Multiply is implemented with a 2-bit per clock, overlapped-scan,
modified Booth algorithm with early-out capability (for minimal die area /future implementations will be faster)
Writeback Bus
Data Bus
H/W Accelerator Interface Bus
X Port
Y Port
Address
Bus
Scale
Sign Ext.
Barrel Shifter
Multiplier
Divider
MUX
MUX
Address MUX
PC
Incrementer
Branch
Adder
Instruction Pipeline
Instruction Decode
Gen. Purpose
Register File
32-bits x 16
Register File
32-bits x 16
Register File
32-bits x 13
Alternate
Control
Adder/Logical
Priority Encoder/Zero Detect
Result MUX
Immediate
MUX
Data Calculation
Address Generation
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