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參數(shù)資料
| 型號(hào)： | M. CORE |
| 廠商： | Motorola, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 高度集成，低功耗，32位微控制器 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大小： | 57K |
| 代理商： | M. CORE |
MOTOROLA
MCORE ARCHITECTURAL INFORMATION
3
to reduce execution time for operations with small multipliers. Divide is implemented with a 1-bit per clock
early-in algorithm. A Find-First-One unit operates in a single clock cycle.
The Program Counter Unit has a PC incrementer and a dedicated Branch Address Adder to minimize delays
during change of flow operations. Branch target addresses are calculated in parallel with branch instruction
decode, with a single pipeline bubble for taken branches and jumps, resulting in an execution time of two
clocks. Conditional Branches which are not taken execute in a single clock.
Memory load and store operations are provided for byte, halfword and word (32-bit) data with automatic zero
extension of byte and halfword load data. These instructions can execute in two clock cycles. Load and store
multiple register instructions allow low overhead context save and restore operations; these instructions can
execute in (N+1) clock cycles, where N is the number of registers to transfer.
A single Condition/Code Carry (C) bit is provided for condition testing and for use in implementing arithmetic
and logical operations greater than 32-bits. Typically, the C bit is set only by explicit test/comparison
operations, not as a side-effect of normal instruction operation. Exceptions to this rule occur for specialized
operations where it is desirable to combine condition setting with actual computation.
A 16-entry Alternate register file is provided to support low overhead interrupt exception processing, and both
vectored and autovectored interrupts are supported by the CPU.
POWER MANAGEMENT FEATURES
The MCORE processor was designed for industry-leading power efficiency. The instruction set and the
machine were designed to effectively access internal and external memory which is where a major portion of
the chip and system’s power consumption can be attributed. Since the MCORE is a 16-bit instruction
machine, it can efficiently interface to external memory through a 16-bit interface. MCORE 16-bit instruction
mapping gives the user a compact memory image as well, which minimizes the number of accesses to both
internal and external memory.
Both static and dynamic power-enhancing features are included in the architecture and implementation. In
terms of the MCORE architecture, three instructions were added to allow the system designer an avenue to
optimize his design with various power saving modes. As defined by MCORE, these instructions are WAIT,
DOZE, and STOP. The functionality of these modes are not dictated by the core but are configured by an
external power management module. The MCORE processor core provides output signals associated with
the execution of each of these instructions that may be monitored by external logic to control operation of the
core as well as the rest of the system.
The first implementation of MCORE is optimized for power consumption. The MCORE has a compact die
area of 2.2 mm sq. in 0.36 (L effective) micron CMOS technology. The logic has been minimized, as well as
the routing capacitance. Gated clocks played a major role in minimizing unnecessary or spurious bus
transitions in the data path portion of the design.
CODE DENSITY
The MCORE engine minimizes the overhead memory system by using (relatively) short 16-bit instruction
encoding. This choice significantly lowers the memory bandwidth needed to sustain a high rate of instruction
execution. The careful selection of instruction for MCORE, allows for a compact data structure and a small
overall memory footprint for the MCORE architecture. MCORE supports 8, 16 and 32-bit data, but is highly
optimized for use out of 16-bit off-chip memory. This allows a design based around MCORE to use less
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| MCOS15C2425M RI-GREY | 制造商:Farnell / Pro-Power 功能描述:CABLE 24AWG SCRN 15CORE 25M 制造商:pro-power 功能描述:CABLE, 24AWG, SCRN, 15CORE, 25M 制造商:pro-power 功能描述:SHLD MULTICOND CABLE, 15COND, 24AWG, 82FT, 300V, Reel Length (Imperial):82ft, Reel Length (Metric):25m, No. of Conductors:15, Conductor Size AWG:24AWG, Voltage Rating:300V, No. of Max Strands x Strand Size:7 x 0.2mm , RoHS Compliant: Yes |
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