- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384634 > LUC4AB01 (Lineage Power) ATM Buffer Manager (ABM)(ATM緩沖管理器 (ABM)) PDF資料下載
參數(shù)資料
| 型號： | LUC4AB01 |
| 廠商： | Lineage Power |
| 英文描述： | ATM Buffer Manager (ABM)(ATM緩沖管理器 (ABM)) |
| 中文描述： | 緩沖區(qū)管理器自動柜員機(jī)（ABM）的（自動柜員機(jī)緩沖管理器（反導(dǎo)條約）） |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 182K |
| 代理商： | LUC4AB01 |
4
Lucent Technologies Inc.
Advance Product Brief
March 1997
ATM Buffer Manager (ABM)
LUC4AB01
S
LUCENT TECHNOLOGIES—PROPRIETARY
Use pursuant to Company Instructions
Description
(continued)
UTOPIA II “Plus” Interface (UTOP)
UTOP performs operations necessary to allow full-
duplex communication between the ABM and ALM (or
an external user proprietary device). It follows the UTO-
PIA II master protocol for 16-bit transfers described in
UTOPIA Level 2, V1.0, except that cell lengths may be
greater than 54 bytes. Every time-slot UTOP is capable
of performing an ingress receive operation and an
egress transmit operation.
Ingress Receive Operation
UTOP is capable of polling only one slave device on
the IWDATA[15:0] bus. It polls this slave device (e.g.
ALM) by driving IWADDR[4:0] with the user-pro-
grammed address located in CFG2_reg[12:8]. If the
slave device (e.g. ALM) has a cell available, it responds
by driving IWCLAV active one cycle later. The transfer
continues as described in UTOPIA Level 2, V1.0. The
cell is written into a FIFO and an internal cell available
is asserted to the ingress queue processor (IQP). Par-
ity is
not
checked on the incoming ingress cell.
Egress Transmit Operation
UTOP is capable of polling up to 31 MPHY ports on the
ERDATA[15:0] bus. Each time-slot UTOP polls one of
these ports in the slave device with the address taken
from the egress MPHY rate schedule. If the slave
device can accept a complete cell, it will respond by
driving ERCLAV active one cycle later. The transfer
continues as described in UTOPIA Level 2, V1.0. If the
port is busy, no cell is transmitted. See egress queue
processor (EQP) for details on the remainder of egress
transmit operation.
Ingress Queue Processor (IQP)
The IQP stores received cells in an ingress buffer
located in external cell data RAM. It queues and sched-
ules cells for transmission to the switch fabric interface
(VTOP). The stored cells are organized into N output
port queues (for N x N switch fabrics), with four delay
priorities (or subqueues) per queue. Each queue is
structured in FIFO order. Any one or set of several
delay priority subqueues can be backpressured individ-
ually by an external switch fabric (fabric backpressure)
to stop traffic from that subqueue to the fabric. The cur-
rent fabric backpressure status is maintained for each
subqueue and is completely updated at least every four
time slots (depending on fabric size) using the fabric
backpressure bitmap received in the egress cell
stream. The IQP also maintains thresholds and accu-
mulates various cell and queue statistics.
Processing of Ingress Cells Received from the
MPHYs
Ingress cell processing is activated when a cell is
received by UTOP. The IQP uses the destination queue
number and delay priority fields (QNR & DLP) in the
local header of the incoming cell (see the data formats
section) to look up the current length of the target
queue. This queue length is then compared with the
applicable ingress thresholds (CLP1, CLP0+1, EPD
and IBP_OVR). If a threshold is exceeded, then the cell
is dropped (except for the IBP_OVR, which sets a sta-
tus bit). Otherwise, the cell is linked to the target queue
at the ingress buffer location obtained from the Ingress
free list. The IQP requires the user to initialize the
ingress free list as a linked list of pointers (organized as
a LIFO stack) to free ingress memory locations. Vari-
ous individual statistic counters are updated.
An ingress queue may be disabled. Cells may be
drained from a disabled queue but cells directed to a
disabled queue are discarded. Discarded cells from
disabled queues are not included in the accumulation
of statistics. Queues are disabled by a configuration
register (IQenable[0:2]_reg) written by the micropro-
cessor.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LUC4AC01 | ATM Crossbar Element (ACE)(ATM縱橫元件（ACE）) |
| LUC4AS01 | ATM Switch Element (ASX)(ATM開關(guān)元件) |
| LUC4AU01 | ATM Layer UNI Manager (ALM)(ATM 層UNI管理器(ALM)) |
| LVSP60 | Blade Terminal & Special Purpose Fuses - Surge Fuses |
| LVSP80 | Blade Terminal & Special Purpose Fuses - Surge Fuses |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LUC4AB01388BAC4-DB | 制造商:Agere Systems 功能描述: |
| LUC4AB01BAC4DB | 制造商:LUCENT 功能描述:* |
| LUC4AS01-BC7-DB | 制造商:Agere Systems 功能描述: |
| LUC4AU01SC5DB | 制造商:LUCENT 功能描述:* |
| LUC4AU01-SC5-DB | 制造商:Agere Systems 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。